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1 of 169 rev: 021805 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the DS33Z11 extends a 10/100 ethernet lan segment by encapsulating mac frames in hdlc or x.86 (laps) for transmission over a pdh/tdm data stream. the serial link supports bidirectional- synchronous interconnect up to 52mbps over xdsl, t1/e1/j1, t3/e3, v.35/optical, oc-1/ec-1, or sonet/sdh tributary. the device performs store-and-forward of packets with full wire-speed transport capability. the built-in committed information rate (cir) controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps. the DS33Z11 can operate with an inexpensive external processor, eeprom or in a stand-alone hardware mode. functional diagram features 10/100 ieee 802.3 ethernet mac (mii and rmii) half/full duplex with automatic flow control 52mbps synchronous tdm serial port with independent transmit and receive timing hdlc/laps encapsulation with programmable fcs and interframe fill committed information rate controller provides fractional allocations in 512kbps increments programmable bert for serial (tdm) interface external 16mb, 100mhz sdram buffering parallel microprocessor interface spi interface and hardware mode for operation without a host processor also available in a 100-ball, 10mm csbga?the hardware/spi mode-only ds33zh11 1.8v operation with 3.3v tolerant i/o ieee 1149.1 jtag support feature highlights continued on page 8 . applications transparent lan service lan extension ethernet delivery over t1/e1/j1, t3/e3, oc-1/ec-1, g.shdsl, or hdsl2/4 ordering information part temp range pin-package DS33Z11 -40c to +85c 169 csbga ds33zh11 -40c to +85c 100 csbga 10/100 mac sdram mii/rmii prom or c config loader DS33Z11 10/100 ethernet phy serial port transceiver/ serial driver bert hdlc/x.86 mapper DS33Z11 ethernet mapper www.maxim-ic.com
DS33Z11 ethernet mapper 2 of 169 table of contents 1 description .................................................................................................................... .......... 7 2 feature highlights ............................................................................................................. .. 8 2.1 g eneral ............................................................................................................................... ........................8 2.2 s erial i nterface ............................................................................................................................... ..........8 2.3 hdlc ........................................................................................................................... ................................8 2.4 c ommitted i nformation r ate (cir) c ontroller ......................................................................................8 2.5 x.86 s upport ............................................................................................................................... ...............8 2.6 sdram i nterface ............................................................................................................................... ........9 2.7 mac i nterface ............................................................................................................................... .............9 2.8 m icroprocessor i nterface .......................................................................................................................9 2.9 s erial spi i nterface ?m aster m ode o nly ..............................................................................................9 2.10 d efault c onfigurations ............................................................................................................................9 2.11 t est and d iagnostics ............................................................................................................................... ..9 2.12 s pecifications c ompliance ......................................................................................................................10 3 applications................................................................................................................... ........ 11 4 acronyms and glossary................................................................................................... 14 5 major operating modes .................................................................................................... 15 6 block diagrams ................................................................................................................. ... 16 7 pin descriptions ............................................................................................................... .... 17 7.1 p in f unctional d escription .....................................................................................................................17 8 functional d escript ion..................................................................................................... 29 8.1 p rocessor i nterface ............................................................................................................................... 29 8.1.1 read-write/data strobe modes ................................................................................................... .......30 8.1.2 clear on read .................................................................................................................. ...................30 8.1.3 interrupt and pin modes........................................................................................................ ..............30 8.2 spi s erial eeprom i nterface ................................................................................................................30 8.3 clock structure ................................................................................................................ ...............31 8.3.1 serial interface clock modes ................................................................................................... ...........33 8.3.2 ethernet interface clock modes................................................................................................. .........33 8.4 r esets a nd l ow p ower m odes ...............................................................................................................34 8.5 i nitialization and c onfiguration .............................................................................................................35 8.6 g lobal r esources ............................................................................................................................... ....35 8.7 p er -p ort r esources ............................................................................................................................... 35 8.8 d evice i nterrupts ............................................................................................................................... .....36 8.9 s erial i nterface ............................................................................................................................... ........38 8.10 c onnections and q ueues .........................................................................................................................38 8.11 a rbiter ............................................................................................................................... .......................39 8.12 f low c ontrol ............................................................................................................................... ............40 8.12.1 full-duplex flow control....................................................................................................... ..............41 8.12.2 half duplex flow control ....................................................................................................... ..............42 8.12.3 host-managed flow control ...................................................................................................... ..........42 8.13 ethernet i nterface p ort .....................................................................................................................43 8.13.1 dte and dce mode ............................................................................................................... ............45 8.14 e thernet mac ............................................................................................................................ ..............46 8.14.1 mii mode options ............................................................................................................... .................48 8.14.2 rmii mode...................................................................................................................... .....................48 8.14.3 phy mii management block and mdio interface...............................................................................49 8.15 bert........................................................................................................................... ...............................50 8.15.1 receive data interface......................................................................................................... ...............50 8.15.2 repetitive pattern synchronization ............................................................................................. ........51
DS33Z11 ethernet mapper 3 of 169 8.15.3 pattern monitoring............................................................................................................. ..................52 8.15.4 pattern generation............................................................................................................. .................52 8.16 t ransmit p acket p rocessor ...................................................................................................................53 8.17 r eceive p acket p rocessor .....................................................................................................................54 8.18 x.86 e ncoding and d ecoding ...................................................................................................................56 8.19 c ommitted i nformation r ate c ontroller ..............................................................................................59 8.20 h ardware m ode ............................................................................................................................... .........61 9 device registers ............................................................................................................... ... 65 9.1 r egister b it m aps ............................................................................................................................... .....66 9.1.1 global register bit map ........................................................................................................ ..............66 9.1.2 arbiter register bit map ....................................................................................................... ...............67 9.1.3 bert register bit map .......................................................................................................... .............67 9.1.4 serial interface r egister bit map .............................................................................................. ..........68 9.1.5 ethernet interface register bit map ............................................................................................ ........70 9.1.6 mac register bit map........................................................................................................... ..............71 9.2 g lobal r egister d efinitions ...................................................................................................................73 9.3 a rbiter r egisters ............................................................................................................................... .....80 9.3.1 arbiter register bit descriptions .............................................................................................. ...........80 9.4 bert r egisters ............................................................................................................................... ........81 9.5 s erial i nterface r egisters .....................................................................................................................88 9.5.1 serial interface transmi t and common registers ..............................................................................88 9.5.2 serial interface transmit register bit descriptions ............................................................................ 88 9.5.3 transmit hdlc processor registers.............................................................................................. ....89 9.5.4 x.86 registers................................................................................................................. ....................96 9.5.5 receive serial interface ....................................................................................................... ...............98 9.6 e thernet i nterface r egisters .............................................................................................................111 9.6.1 ethernet interface register bit descriptions ................................................................................... ..111 9.6.2 mac registers .................................................................................................................. ................123 10 functional timi ng .............................................................................................................. 139 10.1 f unctional s erial i/o t iming .................................................................................................................139 10.2 mii and rmii i nterfaces .........................................................................................................................140 10.3 spi i nterface m ode and eeprom p rogram s equence ......................................................................142 11 operating parameters .................................................................................................... 144 11.1 t hermal c haracteristics ......................................................................................................................145 11.2 t heta -ja vs . a irflow .............................................................................................................................14 5 11.3 t ransmit mii i nterface ..........................................................................................................................146 11.4 r eceive mii i nterface ............................................................................................................................147 11.5 t ransmit rmii i nterface ........................................................................................................................148 11.6 r eceive rmii i nterface ..........................................................................................................................149 11.7 mdio i nterface ............................................................................................................................... .......150 11.8 t ransmit wan i nterface .......................................................................................................................151 11.9 r eceive wan i nterface .........................................................................................................................152 11.10 sdram t iming ............................................................................................................................... ..........153 11.11 ac c haracteristics ?m icroprocessor b us t iming ............................................................................155 11.12 eeprom i nterface t iming ....................................................................................................................158 11.13 jtag i nterface t iming ...........................................................................................................................159 12 jtag information ............................................................................................................... 160 12.1 jtag tap c ontroller s tate m achine d escription ............................................................................160 12.2 i nstruction r egister .............................................................................................................................16 3 12.2.1 sample:pr eload ................................................................................................................. ........164 12.2.2 bypass ......................................................................................................................... ...................164 12.2.3 extest ......................................................................................................................... ...................164 12.2.4 clamp.......................................................................................................................... ....................164 12.2.5 highz .......................................................................................................................... .....................164 12.2.6 idcode ......................................................................................................................... ...................164
DS33Z11 ethernet mapper 4 of 169 12.3 jtag id c odes ............................................................................................................................... ........165 12.4 t est r egisters ............................................................................................................................... ........165 12.5 b oundary s can r egister .......................................................................................................................165 12.6 b ypass r egister ............................................................................................................................... ......165 12.7 i dentification r egister ..........................................................................................................................165 12.8 jtag f unctional t iming ........................................................................................................................165 13 package information ....................................................................................................... 167 13.1 p ackage o utline d rawing of 169-b all csbga ( view from bottom of device ) .................................167 13.2 p ackage o utline d rawing of 100-b all csbga (ds33zh11 o nly ).....................................................168 14 revision history ............................................................................................................... .. 169
DS33Z11 ethernet mapper 5 of 169 list of figures figure 3-1 ethernet to wan extension (no framing) .............................................................................. ................11 figure 3-2 ethernet to wan ext ension (t1e1 fr aming and liu) .................................................................... ........12 figure 3-3 ethernet to wan ext ension with t3/e3 framing ........................................................................ ............12 figure 3-4 ethernet over dsl ................................................................................................... ................................13 figure 3-5 copper to fiber connection .......................................................................................... ..........................13 figure 6-1 detailed block diagram.............................................................................................. .............................16 figure 7-1 DS33Z11 169- ball csbg a pinout ....................................................................................... ...................27 figure 7-2 ds33zh11 100-ball csbga pinout (hardware or spi mode only) .......................................................28 figure 8-1 clocking for the DS33Z11 ............................................................................................ ...........................32 figure 8-2 device interrupt information flow diagram........................................................................... ..................37 figure 8-3 flow control using pause control frame.............................................................................. .................42 figure 8-4 ieee 802.3 ethernet frame ........................................................................................... .........................43 figure 8-5 configured as dte connect ed to an ethernet ph y in mii mode.......................................................... ..45 figure 8-6 DS33Z11 c onfigured as a dce in mii mode ............................................................................. .............46 figure 8-7 rmii interface...................................................................................................... ....................................48 figure 8-8 mii management frame ................................................................................................ ..........................49 figure 8-9 prbs synchroni zation state diagram .................................................................................. ..................51 figure 8-10 repetitive pattern synchronization state diagram ................................................................... ............52 figure 8-11 laps encoding of mac frames concept................................................................................ .............56 figure 8-12 x.86 encapsulat ion of the mac field................................................................................ .....................57 figure 8-13 cir in the wan transmit path ....................................................................................... ......................60 figure 10-1 tx serial inte rface functional timing .............................................................................. ...................139 figure 10-2 rx serial inte rface functional timing.............................................................................. ...................139 figure 10-3 transmit byte sync functi onal timing ............................................................................... ..................140 figure 10-4 receive byte sync functional timing ................................................................................ .................140 figure 10-5 mii transmi t functional timing..................................................................................... ......................141 figure 10-6 mii transmit half duplex with a collision f unctional timing ........................................................ ......141 figure 10-7 mii receiv e functional timing ...................................................................................... ......................141 figure 10-8 rmii transmit inte rface functional timing .......................................................................... ...............141 figure 10-9 rmii receive inte rface functional timing ........................................................................... ...............142 figure 10-10 spi master functional timing ...................................................................................... .....................142 figure 11-1 transmit mii interface ............................................................................................. ............................146 figure 11-2 receive mii interface timing....................................................................................... ........................147 figure 11-3 transmit rmii interface............................................................................................ ...........................148 figure 11-4 receive rmii interface timing ...................................................................................... ......................149 figure 11-5 mdio timing ........................................................................................................ ...............................150 figure 11-6 transmit wan timing................................................................................................ .........................151 figure 11-7 receive wan timing ................................................................................................. ..........................152 figure 11-8 sdram interface timing............................................................................................. ........................154 figure 11-9 intel bus read timi ng (hwmode = 0, modec = 00) ..................................................................... ..156 figure 11-10 intel bus write timi ng (hwmode = 0, modec = 00) ................................................................... ..156 figure 11-11 motorola bus read timi ng (hwmode = 0, modec = 01)..............................................................157 figure 11-12 motorola bus write ti ming (hwmode = 0, modec = 01)..............................................................15 7 figure 11-13 eeprom in terface timing ........................................................................................... .....................158 figure 11-14 jtag interface timing diagram..................................................................................... ...................159 figure 12-1 jtag func tional bloc k diagram ...................................................................................... ...................160 figure 12-2 tap controller state diagram....................................................................................... ......................163 figure 12-3 jtag f unctional timing............................................................................................. .........................166
DS33Z11 ethernet mapper 6 of 169 list of tables table 2-1 t1-related telecomm unications spec ificat ions ......................................................................... .............10 table 7-1 detailed pin descriptions ............................................................................................ .............................17 table 8-1 clocking options for the ethernet interface .......................................................................... ...................31 table 8-2 reset functions...................................................................................................... ..................................34 table 8-3 registers relat ed to connecti ons and queues .......................................................................... .............39 table 8-4 options for flow control............................................................................................. ..............................40 table 8-5 registers related to setting the ethernet port....................................................................... ..................44 table 8-6 mac control registers................................................................................................ .............................47 table 8-7 mac status registers ................................................................................................. .............................47 table 8-8 hardware mode and typical a pplicat ions ............................................................................... .................61 table 8-9 specific functional def ault values for hardware mode ................................................................. ..........62 table 8-10 hardwa re mode pins .................................................................................................. ............................64 table 9-1 register address map ................................................................................................. .............................65 table 9-2 global r egister bit map.............................................................................................. ..............................66 table 9-3 arbiter r egister bit map ............................................................................................. ..............................67 table 9-4 bert register bit map ................................................................................................ ............................67 table 9-5 serial interf ace register bit map.................................................................................... ..........................68 table 9-6 ethernet interface register bit map .................................................................................. .......................70 table 9-7 mac indirect register bit map ........................................................................................ .........................71 table 10-1 eeprom progr am memory map ........................................................................................... ..............143 table 10-2 eeprom program sequence and exam ple for indirect mac registers.............................................143 table 11-1 recommended dc operating conditions ................................................................................. ...........144 table 11-2 dc electrical characteristics ....................................................................................... .........................144 table 11-3 sdram interface timing.............................................................................................. ........................153 table 12-1 instruction codes for ieee 1149.1 ar chitecture ...................................................................... .............164 table 12-2 id code structure................................................................................................... ..............................165
DS33Z11 ethernet mapper 7 of 169 1 description the DS33Z11 provides interconnection and mapping functionality between ethernet packet systems and wan time-division multiplexed (tdm) systems such as t1/e1/j1, hdsl, and t3/e3. the device is composed of a 10/100 ethernet mac, packet arbiter, committed information rate controller (cir), hdlc/x.86 (laps) mapper, sdram interface, control por ts, and bit error-rate tester (bert). the packet interface cons ists of an ethernet interface using several physical-layer protocols. the ethernet interface can be configured for 10 mbps or 100 mbps service. the DS33Z11 encapsulates ethernet traffic with hdlc or x.86 (laps) to be transmitted over the wan interface. the wan interface also receives encapsulated ethernet packets and transmits the extracted packets over the ethernet port. the wan physical interface supports a serial data stream up to 52 mbps. the wan interface can be seamlessly connected to the dallas semiconductor/maxim t1/e1/j1 framers, line interface units (lius), and single-chip transceivers (scts). the wan interface can also be seamlessly connected to the dallas semiconductor/maxim t3/e3/sts-1 framers, lius, and scts to provide t3, e3, and sts1 connectivity. refer to application note 3411: DS33Z11?ethernet lan to unframed t1/e1 wan bri dge for an example of a complete lan to wan solution. the DS33Z11 is controlled through an 8-bit microcontroller port. a serial eeprom (spi) interface and hardware mode are also included for applications without a host processor. the DS33Z11 has a 100mhz sdram controller and interfaces to a 32-bit wide 128 mbit sdram. the sdram is used to buffer the data from the ethernet and wan ports for transport. the external sdram can accommodate up to 8192 frames with a maximum frame size of 2016 bytes. operation without an external host simplifies and reduces the cost of typical applications such as connectivity to t1/t3 and e1/e3 front ends. the DS33Z11 operates with a 1.8v core supply and 3.3v i/o supply.
DS33Z11 ethernet mapper 8 of 169 2 feature highlights 2.1 general 169-pin csbga package (DS33Z11) 100-pin csbga package for hardware/spi modes only (ds33zh11) 1.8v supply with 3.3v tolerant inputs and outputs ieee 1149.1 jtag boundary scan software access to device id and silicon revision development support includes evaluation kit, dr iver source code, and reference designs 2.2 serial interface supports line speeds up to 52 mbps supports data enable and gapped clocking supports byte synchronization input and output for x.86 applications 2.3 hdlc one hdlc controller engine compatible with polled or interrupt driven environments programmable fcs insertion and extraction programmable fcs type supports fcs error insertion programmable packet size limits (minimum 64 bytes and maximum 2016 bytes) supports bit stuffing/destuffing selectable packet scrambling/descrambling (x 43 + 1) separate fcs errored packet and aborted packet counts programmable inter-frame fill for transmit hdlc 2.4 committed information rate (cir) controller cir rate controller limits transmission of data from the ethernet interface to the serial interface cir granularity at 512 kbps cir averaging for smoothing traffic peaks 2.5 x.86 support programmable x.86 address/control fields for transmit and receive programmable 2-byte protocol (sapi) field for transmit and receive 32 bit fcs transmit transparency processing?7e is replaced by 7d, 5e transmit transparency processing?7d replaced by 7d, 5d receive rate adaptation (7d, dd) is deleted receive transparency processing?7d, 5e is replaced by 7e receive transparency processing?7d, 5d is replaced by 7d receive abort sequence the laps packet is dropped if 7d7e is detect self-synchronizing x 43 + 1 payload scrambling. frame indication due to bad address/control/sapi, fcs error, abort sequence, or frame size longer than preset max
DS33Z11 ethernet mapper 9 of 169 2.6 sdram interface interface for 128 mb, 32-bit wide sdram sdram interface speed up to 100 mhz auto refresh timing automatic precharge master clock provided to the sdram no external components required for sdram connectivity 2.7 mac interface mac port with standard mii (less tx_er) or rmii 10 mbps and 100 mbps data rates configurable dte or dce modes facilitates auto-negotiation by host microprocessor programmable half and full-duplex modes flow control for both half-duplex (back-pressure) and full-duplex (pause) modes programmable maximum mac frame size up to 2016 bytes minimum mac frame size: 64 bytes discards frames greater than programmed maximum mac frame size and runt, non-octet bounded, or bad-fcs frames upon reception configurable for promiscuous broadcast-discard mode. programmable threshold for sdram queues to initiate flow control and status indication mac loopback support for transmit data looped to receive data at the mii/rmii interface 2.8 microprocessor interface 8-bit data bus nonmultiplexed intel and motorola timing modes internal software reset and external hardware reset-input pin global interrupt output pin 2.9 serial spi interface?master mode only provides chip select and clock for external eeprom operation up to 8.33 mhz 4-signal interface 2.10 default configurations default hardware configuration for operation without an external microprocessor hardware modes set for easy connection to t1/t3 e1/e3 wan systems hardware pins provide some flexibility for configuration 2.11 test and diagnostics ieee 1149.1 support programmable on-chip bert patterns include pseudorandom qrss, daly, and user-defined repetitive patterns loopbacks (remote, local, analog, and per-channel loopback)
DS33Z11 ethernet mapper 10 of 169 2.12 specifications compliance the DS33Z11 meets relevant telecommunications specificat ions. the following table provides the specifications and relevant sections that are applicable to the DS33Z11. table 2-1 t1-related telecommunications specifications ieee 802.3-2002?csma/cd access method and physical layer specifications rfc1662?ppp in hdlc-like framing rfc2615?ppp over sonet/sdh x.86?ethernet over laps rmii?industry implementation agreement for ?reduced mii interface,? sept 1997
DS33Z11 ethernet mapper 11 of 169 3 applications the DS33Z11 is designed for use in the following applications: transparent lan service lan extension ethernet delivery over t1/e1/j1, t3/e 3, oc-1/ec-1, g.shdsl, or hdsl2/4 refer also to application note 3411: DS33Z11?ethernet lan to unframed t1/e1 wan bridge for an example of a complete lan to wan design. figure 3-1 ethernet to wan extension (no framing) ethernet DS33Z11 rmii, mii 10 base t 100 base t t1/t3 liu ds21q48 ds3154 port hdlc serial stream sdram clock sources
DS33Z11 ethernet mapper 12 of 169 figure 3-2 ethernet to wan exte nsion (t1e1 framing and liu) ethernet DS33Z11 rmii, mii 10 base t 100 base t t1 framer/liu ds21q55 ds26528 port hdlc serial stream sdram clock sources figure 3-3 ethernet to wan ex tension with t3/e3 framing ethernet DS33Z11 rmii, mii 10 base t 100 base t t3 framer/liu ds3154 ds3144 port hdlc serial streams sdram clock sources
DS33Z11 ethernet mapper 13 of 169 figure 3-4 ethernet over dsl ethernet DS33Z11 dsl hdlc serial streams sdram clock sources rmii, mii 10 base t 100 base t figure 3-5 copper to fiber connection ethernet DS33Z11 rmii mii fiber phy hdlc serial streams sdram clock sources optical i/f & connector
DS33Z11 ethernet mapper 14 of 169 4 acronyms and glossary bert: bit error-rate tester dce: data communication interface dte: data terminating interface fcs: frame check sequence hdlc: high-level data link control mac: media access control mii: media independent interface rmii: reduced media independent interface wan: wide area network note 1: previous versions of this document used the term ?subscriber? to refer to the ethernet interface function. the register names have been allowed to remain with a ?su.? prefix to avoid register renaming. note 2: previous versions of this document used the term ?line? to refer to the serial interface. the register names have been allowed to remain with a ?li.? prefix to avoid register renaming. note 3: the terms ?transmit queue? and ?receive queue? are with respect to the ethernet interface. the receive queue is the queue for the data that arrives on the mii/rmii interface, is processed by the mac and stored in the sdram. transmit queue is for data that arrives from the serial port, is processed by the hdlc and stored in the sdram to be sent to the mac transmitter.
DS33Z11 ethernet mapper 15 of 169 5 major operating modes the DS33Z11 has three major modes of operation: microprocessor controlled, eeprom initialized, and hardware mode. microprocessor control is possible through the 8-bit parallel control port. more information on microprocessor control is available in section 8.1 . eeprom initialization is enabled by the built-in spi master that reads a serial eeprom connected to the spi port after device reset and initializes the device. more in formation on eeprom operation is available in section 8.2 . hardware mode allows configuration of the device without a host microprocessor or eeprom. more information on hardware mode is available in section 8.20 .
DS33Z11 ethernet mapper 16 of 169 6 block diagrams figure 6-1 detailed block diagram mac rmii mii sdram interface buffer dev div by 2,4,12 output clocks 25,50 mhz 100 mhz oscillator sysclki sdclko eprom spi_sclk (max 8.33mhz) buffer dev div by 1,2,4,10 output clocks: 50,25 mhz,2.5 mhz 50 or 25 mhz oscillator tx_clk1 rx_clk1 tclki1 rclki1 ref_clko 50 or 25 mhz mdc ref_clki sdram hdlc + serial interface cir line 1 arbiter x.86 tser rser rxd txd microport jtag
DS33Z11 ethernet mapper 17 of 169 7 pin descriptions 7.1 pin functional description note that all digital pins are io pins in jtag mode. this feature increases the effectiveness of board level atpg patterns. jtag pins are not available on the hardware mode/spi-only ds33zh11 (10mm csbga) note: i = input; o = output; ipu = input, with pullup; oz = output, with tri-state; io = bidirectional pin; ioz = bidirectional pin, with tri-state table 7-1 detailed pin descriptions name pin # DS33Z11 csbga (169) pin # ds33zh11 bga(100) type function serial interface io pins tclki f1 b1 i serial interface tran smit clock input: the clock reference for tser, which is output on the rising edge of the clock. tclki supports gapped clocking, up to a maximum frequency of 52 mhz. tser f2 a2 o transmit serial data output: output on the rising edge of tclki. selective clock periods can be skipped for output of tser dependent on the tden settings or gapped clock input (tclki). the maximum data rate is 52 mbps. tden/ tbsync f5 ? io transmit data enable (input): the transmit data enable is programmable to selectively block/enable the transmit data. the tden signal must occur one clock edge prior to the affected data bit. the active polarity of tden is programmable in register li.tslcr. it is recommended for both t1/e1 and t3/e3 applications that use gapped clocks. the tden signal is provided for interfacing to framers that do not have a gapped clock facility. transmit byte sync (output): this output can be used by an external serial to parallel to convert tser stream to byte wide data. this output indicates the last bit of the byte data sent serially on tser. this signal is only active in the x.86 mode. note that while in hardware mode with hdlc (non x.86) operation, this pin must be tied high. rclki g2 b2 i serial interface receive clock input: reference clock for receive serial data on rser. gapped clocking is supported, up to the maximum rclki frequency of 52 mhz. rser h1 b3 i receive serial data input: receive serial data arrives on the rising edge of the clock.
DS33Z11 ethernet mapper 18 of 169 name pin # DS33Z11 csbga (169) pin # ds33zh11 bga(100) type function rden/ rbsync h2 ? i receive data enable: the receive data enable is programmable to block the receive data. the rden must be coincident with the rser data bit to be blocked or enabled. the active polarity of rden is programmable in register li.rslcr. it is recommended for both t1/e1 and t3/e3 applications that use gapped clocks. the rden signal is provided for interfacing to framers that do not have a gapped clock facility. receive byte sync hronization input: provides byte synchronization input to x.86 decoder. this signal will go high at the first bit of the byte as it arrives. this signal can occur at maximum rate every 8 bits. note that a long as the z11 receives one rbsync indicator. the x.86 receiver will determine the byte boundary. hence the z11 does not require a continuous 8-bit sync indicator. a new sync pulse is required if the byte boundary changes. note that while in hardware mode with hdlc (non x.86) operation, this pin must be tied high. mii/rmii port ref_clk d13 ? i reference clock (rmii and mii): when in rmii mode, all signals from the phy are synchronous to this clock input for both transmit and receive. this required clock can be up to 50 mhz and should have 100 ppm accuracy. when in mii mode in dce operation, the DS33Z11 uses this input to generate the rx_clk and tx_clk outputs as required for the ethernet phy interface. when the mii interface is used with dte operation, this clock is not required and should be tied low. ref_clko e13 g10 o reference clock output (rmii and mii): a derived clock output up to 50 mhz, generated by internal division of the sysclki signal. frequency accuracy of the ref_clko signal will be proportional to the accuracy of the user- supplied sysclki signal. this output can be used for the rmii/mii interface clock by external connection to ref_clk. this capability eliminates the need for an additional 50 mhz (rmii) or 25 mhz (mii) phy reference oscillator. see section 8.3.2 for more information. tx_clk a8 a6 io transmit clock (mii): timing reference for tx_en and txd[3:0]. the tx_clk frequency is 25 mhz for 100 mbps operation and 2.5 mhz for 10 mbps operation. in dte mode, this is a clock input provided by the phy. in dce mode, this is an output derived from ref_clk providing 2.5 mhz (10 mbps operation) or 25 mhz (100 mbps operation).
DS33Z11 ethernet mapper 19 of 169 name pin # DS33Z11 csbga (169) pin # ds33zh11 bga(100) type function tx_en e10 b6 o transmit enable (mii): this pin is asserted high when data txd [3:0] is being provided by the DS33Z11. the signal is deasserted prior to the first nibble of the next frame. this signal is synchronous with the rising edge tx_clk. it is asserted with the first bit of the preamble. transmit enable (rmii): when this signal is asserted, the data on txd [1:0] is valid. this signal is synchronous to the ref_clk. txd[0] b9 a8 txd[1] c9 b7 txd[2] d9 b8 txd[3] e9 a9 o transmit data 0 through 3(mii): txd [3:0] is presented synchronously with the rising edge of tx_clk. txd [0] is the least significant bit of the data. when tx_en is low the data on txd should be ignored. transmit data 0 through 1(rmii): two bits of data txd [1:0] presented synchronously with the rising edge of ref_clk. rx_clk a10 b10 io receive clock (mii): timing reference for rx_dv, rx_err and rxd[3:0], which are clocked on the rising edge. rx_clk frequency is 25 mhz for 100 mbps operation and 2.5 mhz for 10 mbps operation. in dte mode, this is a clock input provided by the phy. in dce mode, this is an output derived from ref_clk providing 2.5 mhz (10 mbps operation) or 25 mhz (100 mbps operation). rxd[0] b11 d9 rxd[1] c11 d10 rxd[2] d11 c9 rxd[3] a11 c10 i receive data 0 through 3(mii): four bits of received data, sampled synchronously with the rising edge of rx_clk. for every clock cycle, the phy transfers 4 bits to the DS33Z11. rxd[0] is the least significant bit of the data. data is not considered valid when rx_dv is low. receive data 0 through 1(rmii): two bits of received data, sampled synchronously with ref_clk with 100 mbps mode. accepted when crs_dv is asserted. when configured for 10 mbps mode, the data is sampled once every 10 clock periods. rx_dv d10 a10 i receive data valid (mii): this active high signal indicates valid data from the phy. the data rxd is ignored if rx_dv is not asserted high. rx_crs/ crs_dv c8 c8 i receive carrier sense (mii): should be asserted (high) when data from the phy (rxd[3:0) is valid. for each clock pulse 4 bits arrive from the phy. bit 0 is the least significant bit. in dce mode, connect to v dd . carrier sense/receive data valid (rmii): this signal is asserted (high) when data is valid from the phy. for each clock pulse 2 bits arrive from the phy. in dce mode, this signal must be grounded.
DS33Z11 ethernet mapper 20 of 169 name pin # DS33Z11 csbga (169) pin # ds33zh11 bga(100) type function rx_err b12 b9 i receive error (mii): asserted by the mac phy for one or more rx_clk periods indicating that an error has occurred. active high indicates receive code group is invalid. if crs_dv is low, rx_err has no effect. this is synchronous with rx_clk. in dce mode, this signal must be grounded. receive error (rmii): signal is synchronous to ref_clk. col_det b13 ? i collision detect (mii): asserted by the mac phy to indicate that a collision is occurring. in dce mode this signal should be connected to ground. this signal is only valid in half duplex mode, and is ignored in full duplex mode mdc c12 ? o management data clock (mii): clocks management data between the phy and DS33Z11. the clock is derived from the ref_clk, with a maximum frequency is 1.67 mhz. the user must leave this pin unconnected in the dce mode. mdio c13 ? io mii management data io (mii): data path for control information between the phy and DS33Z11. when not used, pull to logic high externally through a 10k resistor. the mdc and mdio pins are used to write or read up to 32 control and status registers in 32 phy controllers. this port can also be used to initiate auto-negotiation for the phy. the user must leave this pin unconnected in the dce mode. micro port/spi a0/breo a1 potential future revision to add on ball a5 i address bit 0: address bit 0 of the microprocessor interface. least significant bit breo (hardware mode): used in hardware mode to reverse the ordering of hdlc transmit and receive functions. active high input. when 0, the first bit received is the msb. when 1, bit the first bit received is the lsb. the software registers used for control of this function are li.rppcl and li.tppcl. a1/scd b1 potential future revision to add on ball d8 ? address bit 1: address bit 1 of the microprocessor interface. scd (hardware mode): used in hardware mode to disable x 43 +1 bit scrambling for both the transmit and receive paths. applies to hdlc and x.86 transport. when 1, x 43 +1 scrambling is disabled. when 0, x 43 +1 scrambling is enabled. the software registers used for control of this function are li.rppcl and li.tppcl.
DS33Z11 ethernet mapper 21 of 169 name pin # DS33Z11 csbga (169) pin # ds33zh11 bga(100) type function a2/x86ed a2 potential future revision to add on ball b4 ? address bit 2: address bit 2 of the microprocessor interface. x86ed (hardware mode): when in hardware mode, setting this pin high enables x.86 encapsulation for both the transmit and receive data. when 0, hdlc encapsulation is used. the register used to control this function in software mode is li.tx86ede. a3 b2 ? ? address bit 3: address bit 3 of the microprocessor interface. a4 c2 ? ? address bit 4: address bit 4 of the microprocessor interface. a5 a3 ? ? address bit 5: address bit 5 of the microprocessor interface. a6 b3 ? ? address bit 6: address bit 6 of the microprocessor interface. a7 c3 ? ? address bit 7: address bit 7 of the microprocessor interface. a8 a4 ? ? address bit 8: address bit 8 of the microprocessor interface. a9 b4 ? ? address bit 9: address bit 9 of the microprocessor interface. most significant bit. d0/mosi a5 e8 ioz data bit 0: bi-directional data bit 0 of the microprocessor interface. least significant bit. not driven when cs = 1 or rst = 0. master out slave in (spi mode): data stream that provides the instruction and address information to the external eeprom when in spi master mode. mosi is updated on the rising edge when ckpha is set high, and on the falling edge when set low. d1/miso a6 e9 ioz data bit 1: bidirectional data bit 1 of the microprocessor interface. not driven when cs = 1 or rst = 0. master in slave out (spi mode): data path from the spi eeprom to the DS33Z11. must be synchronous with spick. the serial eeprom spi interface will provide data to the DS33Z11, msb first. miso is sampled on the falling edge when ckpha is set high, and on the rising edge when set low. d2/spick a7 e10 ioz data bit 2: bidirectional data bit 2 of the microprocessor interface. not driven when cs = 1 or rst = 0. spick: provides clocking for spi transactions. d3 b5 ? ioz data bit 3: bidirectional data bit 3 of the microprocessor interface. not driven when cs = 1 or rst = 0. d4 b6 ? ioz data bit 4: bidirectional data bit 4 of the microprocessor interface. not driven when cs = 1 or rst = 0. d5 b7 ? ioz data bit 5: bidirectional data bit 5 of the microprocessor interface. not driven when cs = 1 or rst = 0.
DS33Z11 ethernet mapper 22 of 169 name pin # DS33Z11 csbga (169) pin # ds33zh11 bga(100) type function d6 c5 ? ioz data bit 6: bidirectional data bit 6 of the microprocessor interface. not driven when cs = 1 or rst = 0. d7 c6 ? ioz data bit 7: bidirectional data bit 7 of the microprocessor interface. most significant bit. cs = 1 or rst = 0. spi_cs b8 b5 o active-low spi chip select: provides the chip select to the external eeprom, when the spi port is in master mode. ckpha f6 ? i spi clock phase: miso is sampled on the falling edge when ckpha is set high, and on the rising edge when set low. mosi is updated on the rising edge when ckpha is set high, and on the falling edge when set low. cs c1 ? i active-low chip select: this pin must be taken low for read/write operations. when cs is high, the rd/ds and wr signals are ignored. rd/ds e1 ? i active-low read-data strobe (intel mode): the DS33Z11 drives the data bus (d0-d7) with the contents of the addressed register while rd and cs are both low. active-low data strobe (motorola mode): used to latch data through the microprocessor interface. ds must be low during read and write operations. wr /r w e2 ? i active-low write (intel mode): the DS33Z11 captures the contents of the data bus (d0-d7) on the rising edge of wr and writes them to the addressed register location. cs must be held low during write operations. read write (motorola mode): used to indicate read or write operation. r w must be set high for a register read cycle and low for a register write cycle. int f3 ? oz active-low interrupt output: outputs a logic zero when an unmasked interrupt event is detected. int is deasserted when all interrupts have been acknowledged and serviced. inactive state is programmable in register gl.cr1. rst d8 c1 i active-low reset: an active low signal on this pin resets the internal registers and logic. this pin should remain low until power, sysclki, rx_clk, and tx_clk are stable, then set high for normal operation. this input requires a clean edge with a rise time of 25ns or less to properly reset the device. hwmode d5 a3 i hardware mode: connect to v dd to place the device in hardware mode. modec[1:0] determines the default hardware setting to be used. this pin must be held low for control by a microprocessor or an external eeprom.
DS33Z11 ethernet mapper 23 of 169 name pin # DS33Z11 csbga (169) pin # ds33zh11 bga(100) type function modec[0] d6 ? modec[1] d7 a4 i mode control: software mode options (hwmode = 0) 00 = read/write strobe used (intel mode) 01 = data strobe used (motorola mode) 10 ?spi master mode (external eeprom) 11- reserved. do not use. hardware mode options (hwmode = 1) 00 = default hardware mode. see table 8-8 . 01 = reserved. do not use. 10 = reserved. do not use. 11 = reserved. do not use. note that in the 100-pin csbga (ds33zh11) package, only modec[1] is available to the user. modec[0] is internally connected to v ss . dcedtes a13 ? i dce or dte selection: the user must set this pin high for dce mode selection or low for dte mode. this input affects operation in both software and hardware mode. in dce mode, the DS33Z11 mac port can be directly connected to another mac. in dce mode, the transmit clock (tx_clk) and receive clock (rx_clk) are output by the DS33Z11. note that there is no software bit selection of dcedtes. note that dce mode is only relevant when the mac interface is in mii mode. rmiimiis c4 ? i rmii or mii selection: set high to configure the mac for rmii interfacing. set low for mii interfacing. fullds a9 ? i full duplex selection (hardware mode): when in hardware mode, this pin selects full duplex mac operation when set high. if low, the mac will operate in half duplex mode. in software mode, this pin has no effect and duplex selection is controlled in the su.gcr register. h10s b10 ? i 100mb/10mb (hardware mode): when in hardware mode, this pin selects the packet phy data rate. set high for 100 mbps. set low for the mii/rmii interface to run at 10 mbps. in the software mode this pin has no effect and the rate selection is controlled in the su.gcr register. note that in the 100-pin csbga (ds33zh11) package, this pin is internally tied to v dd . afcs c10 ? i automatic flow control (hardware mode): when in hardware mode, set high to enable automatic flow control pause and backpressure application. in the software mode this pin has no effect and the rate selection is controlled by the su.gcr register. note that in the 100-pin csbga (ds33zh11) package, this pin is internally tied to v dd .
DS33Z11 ethernet mapper 24 of 169 name pin # DS33Z11 csbga (169) pin # ds33zh11 bga(100) type function sdram controller sdata[0] m1 h1 sdata[1] l2 f2 sdata[2] n1 j1 sdata[3] m2 d2 sdata[4] n2 k1 sdata[5] n4 k2 sdata[6] n3 j2 sdata[7] l4 c3 sdata[8] j3 d3 sdata[9] m3 e2 sdata[10] h3 c2 sdata[11] j1 f1 sdata[12] j2 g1 sdata[13] k1 d1 sdata[14] k2 d2 sdata[15] l1 e1 sdata[16] m12 k6 sdata[17] h11 g7 sdata[18] m11 j7 sdata[19] n13 k8 sdata[20] n11 k7 sdata[21] l13 j8 sdata[22] n12 h7 sdata[23] k13 k9 sdata[24] j13 j9 sdata[25] j12 h8 sdata[26] h13 h9 sdata[27] h12 c7 sdata[28] g12 g9 sdata[29] f11 g8 sdata[30] g11 g6 sdata[31] l10 c6 ioz sdram data bus (bits 0 through 31): the 32 pins of the sdram data bus are inputs for read operations and outputs for write operations. at all other times, these pins are high-impedance. note: all sdram operations are controlled entirely by the DS33Z11. no user programming for sdram buffering is required. sda[0] n9 j5 sda[1] n10 k5 sda[2] l11 h6 sda[3] k11 f9 sda[4] l7 c4 sda[5] l8 h4 sda[6] l9 g5 sda[7] l5 g4 sda[8] m5 f8 sda[9] m7 f5 sda[10] m8 h5 sda[11] n8 k4 o sdram address bus 0 through 11: the 12 pins of the sdram address bus output the row address first, followed by the column address. the row address is determined by sda0 to sda11 at the rising edge of clock. column address is determined by sda0-sda9 and sda11 at the rising edge of the clock. sda10 is used as an auto- precharge signal. note: all sdram operations are controlled entirely by the DS33Z11. no user programming for sdram buffering is required.
DS33Z11 ethernet mapper 25 of 169 name pin # DS33Z11 csbga (169) pin # ds33zh11 bga(100) type function sba[0] m6 f7 sba[1] n7 j4 i sdram bank select: these two bits select 1 of 4 banks for the read/write/precharge operations. note: all sdram operations are controlled entirely by the DS33Z11. no user programming for sdram buffering is required. sras k6 k3 o active-low sdram row address strobe: used to latch the row address on rising edge of sdclko. it is used with commands for bank activate, precharge, and mode register write. scas h4 f4 o active-low sdram column address strobe: used to latch the column address on the rising edge of sdclko. it is used with commands for bank activate, precharge, and mode register write. swe m4 g3 o active-low sdram write enable: this output enables write operation and auto precharge. sdmask[0] n6 f3 sdmask[1] g4 e3 sdmask[2] m10 j6 sdmask[3] m9 c5 o sdram mask 0 through 3: when high, a write is done for that byte. the least significant byte is sdata7 to sdata0. the most significant byte is sdata31 to sdata24. sdclko n5 j3 o (4ma) sdram clk out: system clock output to the sdram. this clock is a buffered version of sysclki. sysclki g13 k10 i system clock in: 100mhz system clock input to the DS33Z11, used for internal operation. this clock is buffered and provided at sdclko for the sdram interface. the DS33Z11 also provides a divided version output at the ref_clko pin. a clock supply with 100 ppm frequency accuracy is suggested. sdcs l6 h3 o active-low sdram chip select: this output enables sdram access. queue status qovf c7 ? o queue overflow: this pin goes high when the transmit or receive queue has overflowed. this pin goes low when the high watermark is reached again. this pin functions in both software and hardware mode.
DS33Z11 ethernet mapper 26 of 169 name pin # DS33Z11 csbga (169) pin # ds33zh11 bga(100) type function jtag interface jtrst e6 ? ipu active-low jtag reset: jtrst is used to asynchronously reset the test access port controller. after power-up, a rising edge on jtrst will reset the test port and cause the device io enter the jtag device id mode. pulling jtrst low restores normal device operation. jtrst is pulled high internally via a 10k resistor operation. if boundary scan is not used, this pin should be held low. jtclk d4 ? ipu jtag clock: this signal is used to shift data into jtdi on the rising edge and out of jtdo on the falling edge. jtdo e5 ? oz jtag data out: test instructions and data are clocked out of this pin on the falling edge of jtclk. if not used, this pin should be left unconnected. jtdi e4 ? ipu jtag data in: test instructions and data are clocked into this pin on the rising edge of jtclk. this pin has a 10k pullup resistor. jtms f7 ? ipu jtag mode select: this pin is sampled on the rising edge of jtclk and is used to place the test access port into the various defined ieee 1149.1 states. this pin has a 10k pullup resistor. power supplies v dd3.3 g5?g10, h5?h10 a7, d4? d8, h10 i connect to 3.3v power supply v dd1.8 d2, d3, d12, e3, e11, e12, f4, f10, j4, k4, l3, l12, m13 a1, f6, f10, h2, j10 i connect to 1.8v power supply v ss a12, d1, e7, e8, f8, f9, f12, f13, j5?j11, k3, k5, k7, k8, k9, k10, k12 a5, b4, e4?e7 i connect to the common supply ground
DS33Z11 ethernet mapper 27 of 169 figure 7-1 DS33Z11 169-ball csbga pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 a a0 a2 a5 a8 d0 d1 d2 tx_clk fullds rx_clk rxd3 vss dcedtes b a1 a3 a6 a9 d3 d4 d5 spi_cs txd0 h10s rxd0 rx_err col_det c cs a4 a7 rmiimiis d6 d7 qovf rx_crs txd1 afcs rxd1 mdc mdio d vss vdd1.8 vdd1.8 jtclk hwmode modec0 modec1 rst txd2 rx_dv rxd2 vdd1.8 ref_clk e rd/ds wr/ r w vdd1.8 jtdi jtdo jtrst vss vss txd3 tx_en vdd1.8 vdd1.8 ref_clko f tclki tser int vdd1.8 tden ckpha jtms vss vss vdd1.8 sdata29 vss vss g n.c. rclki n.c. sdmask1 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 sdata30 sdata28 sysclki h rser rden sdata10 scas vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 sdata17 sdata27 sdata26 j sdata11 sdata12 sdata8 vdd1.8 vss vss vss vss vss vss vss sdata25 sdata24 k sdata13 sdata14 vss vdd1.8 vss sras vss vss vss vss sda3 vss sdata23 l sdata15 sdata1 vdd1.8 sdata7 sda7 sdcs sda4 sda5 sda6 sdata31 sda2 vdd1.8 sdata21 m sdata0 sdata3 sdata9 swe sda8 sba0 sda9 sda10 sdmask3 sdmask2 sdata18 sdata16 vdd1.8 n sdata2 sdata4 sdata6 sdata5 sdclko sdmask0 sba1 sda11 sda0 sda1 sdata20 sdata22 sdata19
DS33Z11 ethernet mapper 28 of 169 figure 7-2 ds33zh11 100-ball csbga pinout (hardware or spi mode only) 1 2 3 4 5 6 7 8 9 10 a vdd1.8 tser hwmode modec1 vss (future a0) tx_clk vdd3 txd0 txd3 rx_dv b tclki rclki rser vss (future a2) spi_cs tx_en txd1 txd2 rx_err rx_clk c rst sdata10 sdata7 sda4 sdmask3 sdata31 sdata27 rx_crs rxd2 rxd3 d sdata13 sdata14 sdata8 vdd3 vdd3 vdd3 vdd3 vdd3 (future a1) rxd0 rxd1 e sdata15 sdata9 sdmask1 vss vss vss vss mosi miso spick f sdata11 sdata1 sdmask0 scas sda9 vdd1.8 sba0 sda8 sda3 vdd1.8 g sdata12 sdata3 swe sda7 sda6 sdata30 sdata17 sdata29 sdata28 ref_clko h sdata0 vdd1.8 sdcs sda5 sda10 sda2 sdata22 sdata25 sdata26 vdd3 j sdata2 sdata6 sdclko sba1 sda0 sdmask2 sdata18 sdata21 sdata24 vdd1.8 k sdata4 sdata5 sras sda11 sda1 sdata16 sdata20 sdata19 sdata23 sysclki note that pins a5, d8, and b4 have been reserved for future device enhancements for addition of the signals a0, a1, and a2. these ball assignments will allow for the potential future revision to be placed in application designed for the initial device and maintain the same functionality. note that the jtag pins are not available for use in the ds33zh11 100-pin package.
DS33Z11 ethernet mapper 29 of 169 8 functional description the DS33Z11 provides interconnection and mapping functionality between ethernet packet systems and wan time-division multiplexed (tdm) systems such as t1/e1/j1, hdsl, and t3/e3. the device is composed of a 10/100 ethernet mac, packet arbiter, committed information rate controller (cir), hdlc/x.86(laps) mapper, sdram interface, control ports, and bit error rate tester (bert). the ethernet packet interface supports mii and rmii interfaces allowing dsz33z11 to connect to commercially available ethernet phy and mac devices. the ethernet interface can be configured for 10 mbps or 100 mbps service, in dte and dce configurations. the DS33Z11 mac interface rejects frames with bad fcs and short frames (less than 64 bytes). ethernet frames are queued and stored in external 32- bit sdram. the DS33Z11 sdram controller enables connection to a 128mbit sdram without external glue logic, at clock frequencies up to 100 mhz. the sdram is used for both the transmit and receive data queues. the receive queue stores data to be sent from the packet interface to the wan interface. the transmit queue stores data to be sent from the wan interface to the packet interface. the external sdram can accommodate up to 8192 frames with a maximum frame size of 2016 bytes. the sizing of the queues can be adjusted by software. the user can also program high and low watermarks for each queue that can be used for automatic or manual flow control. the packet data stored in the sdram is encapsulated in hdlc or x.86 (laps) to be transmitted over the wan interface. the device also provides the capability for bit and packet scrambling. the wan interface also receives encapsulated ethernet packets and transmits the extracted packets over the ethernet port. the wan physical interface supports serial data streams up to 52 mbps. the wan serial port can operate with a gapped clock, and can be connected to a framer, electrical liu, optical transceiver, or t/e-carrier transceiver for transmission to the wan. the wan interface can be seamlessly connected to the dallas semiconductor/maxim t1/e1/j1 framers, lius, and scts. the wan interface can also be seamlessly connected to the dallas semiconductor/maxim t3/e3/sts-1 framers, lius, and scts to provide t3, e3, and sts1 connectivity. the DS33Z11 can be configured through an 8-bit microprocessor interface port. a serial eeprom (spi) interface and hardware mode are also included for applications without a host microprocessor. operation without an external host simplifies and reduces the cost of typical applications such as connectivity to t1/t3 and e1/e3 front ends. the DS33Z11 also provides two on-board clock divi ders for the system clock input and reference clock input for the 802.3 interfaces, further reducing the need for ancillary devices. 8.1 processor interface microprocessor control of the DS33Z11 is accomplished through the 20 interface pins of the microprocessor port. the 8-bit parallel data bus can be configured for intel or motorola modes of operation with the two modec[1:0] pins. when modec[1:0] = 00 and hwmode = 0, bus timing is in intel mode, as shown in figure 11-9 and figure 11-10 . when modec[1:0] = 01 and hwmode = 0, bus timing is in motorola mode, as shown in figure 11-11 and figure 11-12 . the address space is mapped through the use of 8 address lines, a0-a7. multiplexed mode is not supported on the processor interface. the chip select ( cs) pin must be brought to a logic low level to gain read and write access to the microprocessor port. with intel timing selected, the read ( rd ) and write ( wr ) pins are used to indicate read and write operations and latch data through the interface. with motorola timing selected, the read-write (r w ) pin is used to indicate read and write operations while the data strobe ( ds ) pin is used to latch data through the interface. the interrupt output pin ( int ) is an open-drain output that will assert a logic-low level upon a number of software maskable interrupt conditions. this pin is normally connected to the microprocessor interrupt input. the register map is shown in table 9-1 .
DS33Z11 ethernet mapper 30 of 169 8.1.1 read-write/data strobe modes the processor interface can operate in either read-write strobe mode or data strobe mode. when modec[1:0] = 00 and hwmode pin = 0 the read-write strobe mode is enabled and a negative pulse on rd performs a read cycle, and a negative pulse on wr performs a write cycle. when modec[1:0] pins = 01 and hwmode pin = 0 the data strobe mode is enabled and a negative pulse on ds when r w is high performs a read cycle, and a negative pulse on ds when r w is low performs a write cycle. the read-write strobe mode is commonly called the ?intel? mode, and the data strobe mode is commonly called the ?motorola? mode. 8.1.2 clear on read the latched status registers will clear on a read access. it is important to note that in a multi-task software environment, the user should handle all status conditions of eac h register at the same time to avoid inadvertently clearing status conditions. the latched status register bits are carefully designed so that an event occurrence cannot collide with a user read access. 8.1.3 interrupt and pin modes the interrupt ( int ) pin is configurable to drive high or float w hen not active. the intm bit controls the pin configuration, when it is set the int pin will drive high when not active. after reset, the int pin is in high-impedance mode until an interrupt source is active and enabled to drive the interrupt pin. 8.2 spi serial eeprom interface the spi interface is a 4 signal serial interface that allows connection to a serial eeprom for initialization information. the DS33Z11 will act as an spi master when configured with modec[1:0] to read from an external serial eeprom. the reading sequence is commenced upon initial reset or rising edge of the rst input pin. the ckpha pin controls the sampling and update edges of the miso and mosi signals. the miso data can be sampled on rising or falling edge of spick. the mosi (maste r out slave in) can be selectively output on the rising or falling edge of spick. the spick is generated by the DS33Z11 at a frequency of 8.33 mhz. this frequency is derived from an external sysclki (100 mhz). the instruction to initiate a read is 0000x011; this is followed by the address location 0. the spi_cs is low till the data addressed ( table 10-1 ) is read and latched. the DS33Z11 will provide the starting address (0000000) and the data is sequentially latched till the last data is read and latched. the mac specific registers, which are addressed indirectly, are written at the end of the normal control registers. more details of the programming sequence an functional timing information can be found in section 10.3 . the indirect registers related to the mac are programmed using a special command format as shown in table 10-2 .
DS33Z11 ethernet mapper 31 of 169 8.3 clock structure the DS33Z11 clocks sources and functions are as follows: serial transmit data (tclki) and serial receive data (rclki) clock inputs are used to transfer data from the serial interface. these clocks can be continuous or gapped. system clock (sysclki) input. used for internal operation. this clock input cannot be a gapped clock. a clock supply with 100 ppm frequency accuracy is suggested. a buffered version of this clock is provided on the sdclko pin for the operation of the sdram. a divided and buffered version of this clock is provided on the spick pin for serial eeprom operation. a divided and buffered version of this clock is provided on ref_clko for the rmii/mii interface. packet interface reference clock (ref_clk) input that can be 25 or 50 mhz. this clock is used as the timing reference for the rmii/mii interface. the user can utilize the built-in ref_clko output clock to drive this input. the transmit and receive clocks for the mii interface (tx_clk and rx_clk). in dte mode, these are input pins and accept clocks provided by an ethernet phy. in the dce mode, these are output pins and will output an internally generated clock to the ethernet phy. the output clocks are generated by internal division of ref_clk. in rmii mode, only the ref_clk input is used. ref_clko is an output clock that is generated by dividing the 100 mhz system clock (sysclki) by 2 or 4. this output clock can be used as an input to ref_clk, allowing the user to have one less oscillator for the system. a management data clock (mdc) output is derived from sysclki and is used for information transfer between the internal ethernet mac and external phy. the mdc clock frequency is 1.67 mhz. the following table provides the different clocking options for the ethernet interface. table 8-1 clocking options for the ethernet interface rmiimiis pin speed dce/ dte ref_clko output ref_clk input rx_clk tx_clk mdc output 0 (mii) 10 mbps dte 25 mhz 25 mhz +/- 100 ppm input from phy input from phy 1.67 mhz 0 (mii) 10 mbps dce 25 mhz 25 mhz +/- 100 ppm 2.5 mhz (output) 2.5 mhz (output) 1.67 mhz 0 (mii) 100 mbps dce 25 mhz 25 mhz +/- 100 ppm 25 mhz (output) 25 mhz (output) 1.67 mhz 1 (rmii) 10 mbps - 50 mhz 50 mhz +/- 100 ppm not applicable not applicable 1.67 mhz 1 (rmii) 100 mbps - 50 mhz 50 mhz +/- 100 ppm not applicable not applicable 1.67 mhz
DS33Z11 ethernet mapper 32 of 169 figure 8-1 clocking for the DS33Z11 mac rmii mii sdram interface buffer dev div by 2,4,12 output clocks 25,50 mhz 100 mhz oscillator sysclki sdclko eprom spi_sclk (max 8.33mhz) buffer dev div by 1,2,4,8,10 output clocks: 50,25 mhz,2.5 mhz 50 or 25 mhz oscillator tx_clk1 rx_clk1 tclki1 rclki1 ref_clko 50 or 25 mhz mdc ref_clki sdram hdlc + serial interface cir line 1 arbiter x.86 tser rser rxd txd microport jtag
DS33Z11 ethernet mapper 33 of 169 8.3.1 serial interface clock modes the serial interface timing is determined by the line clocks. both the transmit and receive clocks (tclki and rclki) are inputs, and can be gapped. 8.3.2 ethernet interface clock modes the ethernet phy interface has several different clocking requirements, depending on the mode of operation. the user has the option of using the internally generated ref_clko output to simplify the system design. table 8-1 outlines the possible clocking modes for the ethernet interface. the buffered ref_clko output is generated by division of the 100 mhz system clock input by the user on sysclki. the frequency of the ref_clko pin is automatically determined by the DS33Z11 based on the state of the rmiimiis pin. the ref_clko output can be used as a ref_clk for the ethernet interface by connecting ref_clko to ref_clk. the ref_clko function can be turned off with the gl.cr1.rfoo bit. in rmii mode, receive and transmit timing is always synchronous to a 50 mhz clock input on the ref_clk pin. the source of ref_clk is expected to be the external phy. the user has the option of using the 50mhz ref_clko output as the timing source for the phy. more information on rmii mode can be found in section 8.14.2 . while using mii mode with dte operation, the mii clocks (rx_clk and tx_clk) are inputs that are expected to be provided by the external phy. while using mii mode with dce operation, the mii clocks (tx_clk and rx_clk) are output by the DS33Z11, and are derived from the 25 mhz ref_clk input. any 25 mhz reference may be used, but the user may choose to use the ref_clko output to avoid adding another system clock. more information on mii mode can be found in section 8.14.1 .
DS33Z11 ethernet mapper 34 of 169 8.4 resets and low power modes the external rst pin and the global reset bit in gl.cr1 create an internal global reset signal. the global reset signal resets the status and control registers on the chip (except the gl.cr1 . rst bit) to their default values and resets all the other flops to their reset values. the processor bus output signals are also placed in high-impedance mode when the rst pin is active (low). the global reset bit (gl.cr1 . rst) stays set after a one is written to it, but is reset to zero when the external rst pin is active or when a zero is written to it. allow 5 milliseconds after initiating a reset condition for the reset operation to complete. the serial interface reset bit in li.rstpd resets all the status and control registers on the serial interface to their default values, except for the li.rstpd . rst bit. the serial interface includes the hdlc encoder/decoder, x86 encoder and decoder and the corresponding serial port. the serial interface reset bit (li.rstpd . rst) stays set after a one is written to it, but is reset to zero when the gl obal reset signal is active or when a zero is written to it. if DS33Z11 is configured to use an external eeprom, the DS33Z11 will provide the startup sequence to read the device settings upon the rising edge of the external rst pin. when using the external eeprom the device is configured within 5 ms. this is dependent on an eeprom clock of 8.33 mhz. the functional timing is provided by figure 10-10 . table 8-2 reset functions reset function location comments hardware device reset rst pin transition from a logic 0 to a logic 1 resets the device. hardware jtag reset jtrst pin resets the jtag test port. global software reset gl.cr1 writing to this bit resets the device. serial interface reset li.rstpd writ ing to this bit resets the serial interface. queue pointer reset gl.c1qpr writing to this bit resets the queue pointers there are several features in the DS33Z11 to reduce power consumption. the reset bit in the li.rstpd and register also place the serial interface in a low-power mode. additionally, the rst pin may be held low indefinitely to keep the entire device in a low-power mode. note that exiting the low-power condition requires re-initialization and configuration.
DS33Z11 ethernet mapper 35 of 169 8.5 initialization and configuration example device initialization sequence: step 1: reset the device by pulling the rst pin low or by using the software reset bits outlined in section 8.4 . clear all reset bits. allow 5 milliseconds for the reset recovery. step 2: check the device id in the gl.idrl and gl.idrh registers. step 3: configure the system clocks. allow the clock system to properly adjust. step 4: initialize the entire remainder of the register s pace with 00h (or otherwise if specifically noted in the register?s definition), including the reserved bits and reserved register locations. step 5: write ffffffffh to t he mac indirect addresses 010ch through 010fh. step 6: setup connection in the gl.con1 register. step 7: configure the serial port register space as needed. step 8: configure the ethernet port register space as needed. step 9: configure the ethernet mac indirect registers as needed. step 10: configure the external ethernet phy through the mdio interface. step 11: clear all counters and latched status bits. step 12: set the queue size in the arbiter and reset the queue pointers for the ethernet and serial interfaces. step 13: enable interrupts as needed. step 14: begin handling interrupts and latched status events. 8.6 global resources in order to maintain software compatibility with the multiport devices in the product family, a set of global registers are located at 0f0h-0ffh. the global registers include global resets, global interrupt status, interrupt masking, clock configuration, and the device id regist ers. see the global register definitions in table 9-2 . 8.7 per-port resources multi-port devices in this product family share a common set of global registers, bert, and arbiter. all other resources are per-port.
DS33Z11 ethernet mapper 36 of 169 8.8 device interrupts figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. when an interrupt occurs, the host can read the global latched status registers gl.lis, gl.sis, gl.bis, and gl.trqis to initially determine the source of the interrupt. the host can then read the li.tqctls, li.tppsrl, li.r ppsrl, li.rx86s, su.qcrls, or bsrl registers to further identify the source of the interrupt(s). in order to maintain software compatibility with the multiport devices in the product family, the global interrupt status and interrupt enable registers have been preserved, but do not need to be used. if gl.trqis is determined to be the interrupt source, the host will then read the li.tppsrl and li.rppsrl registers for the cause of the interrupt. if gl.lis is determined to be the interrupt source, the host will then read the li.tqctls, li.tppsrl, li.rppsrl, and li.rx86s registers for the source of the interrupt. if gl.sis is the source, the host will then read the su.qcrls register for the source of the interrupt. if gl.bis is the source, the host will then read the bsrl register for the source of the interrupt. all global interrupt status register bits are real-time bits that will clear once the appropriate interrupt has been serviced and cleared, as long as no additional, enabled interrupt conditions are present in the asso ciated status register. all latched status bits must be cleared by the host writing a ?1? to the bit location of the interrupt condition that has been serviced. in order for individual status conditions to transmit their status to the next level of interrupt logic, they must be enabled by placing a ?1? in the associated bit location of the correct interrupt enable register. the interrupt enable registers are li.tppsrie, li.rppsrie, li.rx86lsie, bsrie, su.qri e, gl.lie, gl.sie, gl.bie, and gl.trqie. latched status bits that have been enabled via inte rrupt enable registers are allowed to pass their interrupt conditions to the global interrupt status registers. the interrupt enabl e registers allow individual latched status conditions to generate an interrupt, but when set to zero, they do not prevent the latched status bits from being set. therefore, when servicing interrupts, the user should and the latched status with the associated interrupt enable register in order to exclude bits for which the user wished to prevent interrupt service. this architecture allows the application host to periodically poll the latched status bits for non-in terrupt conditions, while using only one set of registers. note the bit-orders of su.qrie and su.qcrls are different. note that the inactive state of the interrupt output pin is configurable. the intm bit in gl.cr1 controls the inactive state of the interrupt pin, allowing selection of a pull-up resistor or active driver . the interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. the latched status bits for the interrupting entity must be read to clear the interrupt. also reading the latched status bit will reset all bits in that register. during a reset condition, interrupts cannot be generated. the interrupts from any source can be blocked at a global level by the placing a zero in the global interrupt enable registers (gl.lie, gl.sie, gl.bie, and gl.trqie). reading the latched status bit for all interrupt generating events will clear the interrupt status bit and interrupt signal will be de-asserted.
DS33Z11 ethernet mapper 37 of 169 figure 8-2 device interrupt information flow diagram receive fcs errored packet 7 receive aborted packet 6 receive invalid packet detected 5 receive small packet detected 4 receive large packet detected 3 receive fcs errored packet count 2 receive aborted packet count 1 receive size violation packet count 0 li.rppsl li.rppsrie 7 6 5 4 3 2 1 transmit errored packet insertion finished 0 li.tppsrl li.tppsrie 7 6 5 4 sapi high is not equal to li.trx86sapih 3 sapi low is not equal to li.trx86sapil 2 control is not equal to li.trx8c 1 address is not equal to li.trx86a 0 li.rx86s li.rx86lsie 7 6 5 4 transmit queue fifo overflowed 3 transmit queue overflow 2 transmit queue for connection exceeded low threshold 1 transmit queue for connection exceeded high threshold 0 li.tqctls li.tqtie 7 6 5 4 receive queue fifo overflowed 3 receive queue overflow 2 receive queue for connection exceeded low threshold 1 receive queue for connection exceeded high threshold 0 su.qcrls su.qrie 7 6 5 4 performance monitor update 3 bit error detected 2 bit error count 1 out of synchronization 0 bsrl bsrie drawing legend: interrupt status registers register name interrupt enable registers register name interrupt pin 7 6 5 4 3 2 1 0 gl.trqis gl.trqie 7 6 5 4 3 2 1 0 gl.lis gl.lie 7 6 5 4 3 2 1 0 gl.sis gl.sie 7 6 5 4 3 2 1 0 gl.bis gl.bie
DS33Z11 ethernet mapper 38 of 169 8.9 serial interface the serial (wan) interface supports time-division multiplexed, serial data input and output up to 52 mbps. the serial interface receives and transmits encapsulated ethernet packets. the serial interface block consists of the physical serial port and hdlc / x.86 engine. the physical interface consists of a transmit data, transmit clock, transmit enable, receive data, receive clock, and rece ive enable. the wan serial port can operate with a gapped clock, and can be connected to a framer, electrical liu, optical transceiver, or t/e-carrier transceiver for transmission to the wan. the wan interface can be seamlessly connected to the dallas semiconductor/maxim t1/e1/j1 framers, lius, and scts such as the ds26401, ds21348, and ds2155. the wan interface can also be seamlessly connected to the dallas semiconductor/maxim t3/e3/sts-1 framers, lius, and scts such as the ds3144 or ds3154 to provide t3, e3, and sts1 connectivity. 8.10 connections and queues the multiport devices in this product family provide bi directional cross-connections between the multiple ethernet ports and serial ports when operating in software mode. a single connection is preserved in this single-port device to provide software compatibility with multi-port devices. the connection will have an associated transmit and receive queue. note that the terms ?transmit queue? and ?receive queue? are with respect to the ethernet interface. the receive queue is for data arriving from ethernet interface to be transmitted to the wan interface. the transmit queue is for data arriving from the wan to be transmitted to the ethernet interface. hence the transmit and receive direction terminology is the same as is used for the ethernet mac port. the user can define the connection and the size of the transmit and receive queues. the size is adjustable in units of 32(by 2048 byte) packets. the external sdram can hold up to 8192 packets of data. the user must ensure that all the connection queues do no exceed this limit. the user also must ensure that the transmit and receive queues do not overlap each other. unidirectional connections are not supported. when the user changes the queue sizes, the connection must be torn down and re-established. when a connection is disconnected all transmit and receive queues associated with the connection are flushed and a ?1? is sourced towards the serial transmit and the hdlc receiver. the clocks to the hdlc are sourced a ?0.? the user can also program high and low watermarks. if the queue size grows past the high watermark, an interrupt is generated if enabled. the registers of relevance are described in table 8-3 . the ar.tqsc1 size provides the size of the transmit queue for the connection. the high watermark will set a latched status bit. the latched status bit will clear when the register is read. the status bit is indicated by li.tqctls.tqhts. interrupts can be enabled on the latched bit events by li.tqtie. a latched status bit (li.tqctls.tqlts) is also set when the queue crosses a low watermark. the receive queue functions in a similar manner. note that the user must ensure that sizes and watermarks are set in accordance with the configuration speed of the ethernet and serial interfaces. the DS33Z11 does not provide error indication if the user creates a c onnection and queue that overwrites data for another connection queue. the user must take care in setting the queue sizes and watermarks. the registers of relevance are ar.rqsc1and su.qcrls. queue size should never be set to 0.
DS33Z11 ethernet mapper 39 of 169 it is recommended that the user reset the queue pointers for the connection after disconnection. the pointers must be reset before a connection is made. if this disconnect/connect procedure is not followed, incorrect data may be transmitted. the proper procedure for setting up a connection follows: set up the queue sizes for both transmit and receive queue (ar.tqsc1 and ar.rqsc1). set up the high/low thresholds and interrupt enables if desired (gl.trqie, li.tqtie, su.qrie) reset all the pointers for the connection desired (gl.c1qpr) set up the connections (gl.con1) if a connection is disconnected, reset the queue pointers after the disconnection. table 8-3 registers related to connections and queues register gl.con1 enables connection between the ethernet interface and the serial interface. note that once connection is set up, then the queues and thresholds can be setup for that connection. ar.tqsc1 size for the transmit queue in number of 32?2k packets. ar.rqsc1 size for the receive queue in number of 32?2k packets. gl.trqie interrupt enable for items related to the connections at the global level gl.trqis interrupt enable status for items related to the connections at the global level li.tqtie enables for the transmit queue crossing high and low thresholds li.tqctls latched status bits for connection high and low thresholds for the transmit queue. su.qrie enables for the receive queue crossing high and low thresholds su.qcrls latched status bits for receive queue high and low thresholds. gl.c1qpr resets the connection pointer. 8.11 arbiter the arbiter manages the transport between the ethernet port and the serial port. it is responsible for queuing and dequeuing packets to a single external sdram. the arbi ter handles requests from the hdlc and mac to transfer data to and from the sdram.
DS33Z11 ethernet mapper 40 of 169 8.12 flow control flow control may be required to ensure that data queues do not overflow and packets are not lost. the DS33Z11 allows for optional flow control based on the queue high watermark or through host processor intervention. there are 2 basic mechanisms that are used for flow control: in half duplex mode, a jam sequence is sent that causes collisions at the far end. the collisions cause the transmitting node to reduce the rate of transmission. in full duplex mode, flow control is initiated by the receiving node sending a pause frame. the pause frame has a timer parameter that determines the pause timeout to be used by the transmitting node. note that the terms ?transmit queue? and ?receive queue? are with respect to the ethernet interface. the receive queue is the queue for the data that arrives on the mii/rmii interface, is processed by the mac and stored in the sdram. transmit queue is for data that arrives from the serial port, is processed by the hdlc and stored in the sdram to be sent to the mac transmitter. the following flow control options are possible: automatic flow control can be enabled in hardware mode by the afcs and fullds pins automatic flow control can be enabled in software mode with the su.gcr.atflow bit. note that the user does not have control over su.macfcr.fce and fcb bits if atflow is set. the mechanism of sending pause or jam is dependent only on the receive queue high threshold. manual flow control can be performed through software when su.gcr.atflow = 0. the host processor must monitor the receive queues and generate pause frames (full duplex) and/or jam bytes through the su.macfcr.fcb, su.gcr.jame, and su.macfcr.fce bits. note that in order to use flow control, the receive queue size (in ar.rqsc1) must be 02h or greater. the receive queue high threshold (in su.rqht) must be set to 01h or greater, but must be less than the queue size. if the high threshold is set to the same value as the queue size, automatic flow control will not be effective. the high threshold must always be set to less than the corresponding queue size. the following table provides all the options on flow control mechanism for DS33Z11. table 8-4 options for flow control hardware mode software mode configuration no flow control half duplex, flow control with respect to su.rqht full duplex, flow control with respect to su.rqht half duplex; manual flow control half duplex; automatic flow control full duplex; manual flow control full duplex; automatic flow control hwmode pin 1 1 1 0 0 0 0 afcs pin 0 1 1 n/a n/a n/a n/a fullds pin 0 0 1 0 0 1 1 atflow bit n/a n/a n/a 0 1 0 1 jame bit n/a n/a n/a controlled by user controlled automatically n/a n/a fcb bit (pause) n/a n/a controlled automatically n/a n/a controlled by user controlled automatically fce bit n/a set to afcs pin = low set to afcs pin = high controlled by user controlled automatically controlled by user controlled automatically pause timer n/a n/a set to 140h n/a n/a programmed by user programmed by user
DS33Z11 ethernet mapper 41 of 169 8.12.1 full-duplex flow control in the software mode automatic flow control is enabled by default. the host processor can disable this functionality with su.gcr.atflow. in hardware mode, the user must apply a logic high level to the afcs pin to enable automatic flow control. the flow control mechanism is governed by the high watermarks (su.rqht). the su.rqlt low threshold can be used as indication that the network congestion is clearing up. the value of su.rqlt does not affect the flow control. when the connection queue high threshold is exceeded the DS33Z11 will send a pause frame with the timer value programmed by the user. see table 8-6 for more information. it is recommended that 80 slots (80 by 64 bytes or 5120 bytes) be used as the standard timer value. the pause frame causes the distant transmitter to ?pause for a time? before starting transmission again. the pause command has a multicast address 01-80-62-00-00-01. the high and low thresholds for the receive queue are configurable by the user but it is recommended that the high threshold be set approximately 96 packets from the maximum size of the queue and the low threshold 96 packets lower than the high threshold. the DS33Z11 will send a pause frame as the queue has crossed the high threshold and a frame is received. pause is sent every time a frame is received in the ?high threshold state?. pause control will only take care of temporary congestion. pause control does not take care of systems where the traffic throughput is too high for the queue sizes selected. if the flow control is not effective the receive queue will eventually overflow. this is indicated by su.qcrls.rqovfl latched bit. if the receive queue is overflowed any new frames will not be received. the user has the option of not enabling automatic flow control. in this case the thresholds and corresponding interrupt mechanism to send pause frame by writing to flow control busy bit in the mac flow control registers su.macfcr.fcb, su.gcr.jame, and su.macfcr. this allows the user to set not only the watermarks but also to decide when to send a pause frame or not based on watermark crossings. on the receive side the user has control over whether to respond to the pause frame sent by the distant end (pcf bit). note that if automatic flow control is enabled the user cannot modify the fce bit in the mac flow control register. on the transmit queue the user has the option of setting high and low thresholds and corresponding interrupts. there is no automatic flow control mechanism for data received from the serial side waiting for transmission over the ethern et interface during times of heavy ethernet congestion.
DS33Z11 ethernet mapper 42 of 169 figure 8-3 flow control us ing pause control frame receive queue growth receive queue high water mark initiate flow control 8 rx data receive queue low water 8.12.2 half duplex flow control half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. the receiving node jams the first 4 bytes of a packet that are received from the mac in order to cause collisions at the distant end. in both 100 mbps and 10 mbps mii/rmii modes, 4 bytes are jammed upon reception of a new frame. note that the jamming mechanism does not jam the current frame that is being received during the watermark crossing, but will wait to jam the next frame after the su.rqht bit is set. if the queue remains above the high threshold, received frames will continue to be jammed. this jam sequence is stopped when the queue falls below the high threshold. 8.12.3 host-managed flow control although automatic flow control is recommended, flow control by the host processor is also possible. by utilizing the high watermark interrupts, the host processor can manually issue pause frames or jam incoming packets to exert backpressure on the transmitting node. pause frames can be initiated with su.macfcr.fcb bit. jam sequences can be initiated be setting su.gcr.jame. the host can detect pause frames by monitoring su.rfsb3.uf and su.rfsb3.cf. jammed frames will be indistinguishable from packet collisions.
DS33Z11 ethernet mapper 43 of 169 8.13 ethernet interface port the ethernet port interface allows for direct connection to an ethernet phy. the interface consists of a 10/100 mbps mii/rmii interface and an ethernet mac. in rmii operation, the interface contains 7 signals with a reference clock of 50 mhz. in mii operation, the interface contains 17 signals and a clock reference of 25 mhz. the DS33Z11 can be configured to rmii or mii interface by the hardware pin rmiimiis. the ref_clko output can be used to source the ref_clk input. if the port is configured for mii in dce mode, ref_clk must be 25 mhz. the DS33Z11 will internally generate the tx_clk and rx_clk outputs (at 25 mhz for 100mbps, 2.5 mhz for 10mbps) required for dce mode from the ref_clk input. in mii mode with dte operation, the tx_clk and rx_clk signals are generated by the phy and are inputs to the DS33Z11. for more information on clocking the ethernet interface, see section 8.3 . the data received from the mii or rmii interface is processed by the internal ieee 802.3 complaint ethernet mac. the user can select the maximum frame size (up to 2016 bytes) that is received with the su.rmfsrh and su.rmfsrl registers. the maximum frame length (in bits) is the number specified in su.rmfsrh and su.rmfsrl multiplied by 8 . any programmed value gr eater than 2016 bytes will result in unpredictable behavior and should be avoided. the maximum frame size is shown in figure 8-4 . the length includes only destination address, source address, vl an tag (2 bytes), type length field, data and crc32. the frame size is different than the 802.3 ?type length field?. frames coming from the ethernet phy or received from the packet processor are rejected if greater than the maximum frame size specified. each ethernet frame sent or received generates status bits (su.tfsh and su.tfsl and su.rfsb0 to su.rfsb3). these are real time status registers and will change as each frame is sent or received. hence they are useful to the user only when one frame is sent or received and the status is associated with the frame sent or received. figure 8-4 ieee 802.3 ethernet frame preamble sfd destination adrs source address type lenght data crc32 7 1 6 6 2 46-1500 4 max frame length the distant end will normally reject the sent frames if jabber timeout, loss of carrier, excessive deferral, late collisions, excessive collisions, under run, deferred or collision errors occur. transmission of a frame under any of theses errors will generate a status bit in su.tfsl, su.tfsh. the DS33Z11 provides user the option to automatically retransmit the frame if any of the errors have occurred through the bit settings in su.tfrc. deferred frames and heartbeat fail have separate resend control bits (su.tfrc.tfbfcb and su.tfrc.tprhbc). if there is no carrier (indicated by the mac transmit packet status), the transmit queue (data from the serial interface to the sdram to ethernet interface) can be selectively flushed. this is controlled by su.tfrc.ncfq.
DS33Z11 ethernet mapper 44 of 169 the mac circuitry generates a frame status for every frame that is received. this real time status can be read by su.rfsb0 to su.rfsb3. note the frame status is t he ?real time? status and hence the value will change as new frames are received. hence the real time status reflects the status in time and may not correspond to the current received frame being processed. this is also true for the transmitted frames. frames with errors are usually rejected by the DS33Z11. the user has the option of accepting frames by settings in receive frame rejection control register (su.rfrc). the user can program whether to reject or accept frames with the following errors: mii error asserted during the reception of the frame dribbling bits occurred in the frame crc error occurred length error occurred?the length indicated by the frame length is inconsistent with the number of bytes received control frame was received. the mode must be full duplex unsupported control frame was received note that frames received that are runt frames or frames with collision will automatically be rejected. in hardware mode any frame received with errors is rejected and any frame transmitted with an error is retransmitted table 8-5 registers related to setting the ethernet port register comment su.tfrc this register determines if the current frame is retransmitted due to various transmit errors su.tfsl and su.tfsh these 2 registers provide the real time status of the transmit frame. only apply to the last frame transmitted. su.rfsb0 to 3 these registers provide the real time st atus for the received frame. only apply to the last frame received. su.rfrc this register provides settings for reception or rejection of frame based on errors detected by the mac. su.rmfsrh and su.rmfsrl the settings for this register provide the maximum size of frames to be accepted from the mii/rmii receive interface. su.maccr this register provides configuration control for the mac
DS33Z11 ethernet mapper 45 of 169 8.13.1 dte and dce mode the ethernet mii/rmii port can be configured for dce or dte mode. when the port is configured for the dte mode it can be connected to an ethernet phy. in dce mode, the port can be connected to mii/rmii mac devices other than an ethernet phy. the dte/dce connections for the DS33Z11 in mii mode are shown in the following 2 figures. in dce mode, the DS33Z11 transmitter is connected to an external receiver and DS33Z11 receiver is connected to an external mac transmitter. the selection of dte or dce mode is done by the hardware pin dcedtes. figure 8-5 configured as dte connected to an ethernet phy in mii mode mac rxd[3:0] rxd[3:0] rx_clk rx_clk rx_err rx_err rx_crs rx_crs col_det col_det ethernet phy tx_en tx_en mdc mdio txd[3:0] txd[3:0] tx_clk DS33Z11 wan dce dte tx_clk mdio mdc rxdv rxdv rx rx tx tx arbiter
DS33Z11 ethernet mapper 46 of 169 figure 8-6 DS33Z11 configured as a dce in mii mode mac txd[3:0] rxd[3:0] tx_clk rx_clk tx_err rx_err tx_en rx_crs col_det col_det dte dce tx_en rxdv mdc mdio txd[3:0] rxd[3:0] tx_clk DS33Z11 wan mac rx_clk rxdv rx_crs mdio mdc rx tx tx rx arbiter 8.14 ethernet mac indirect addressing is required to access the mac regist er settings. writing to the mac registers requires the su.macwd0-3 registers to be written with 4 bytes of data. the address must be written to su.macawl and su.macawh. a write command is issued by writing a zero to su.macrwc.mcrw and a one to su.macrwc.mcs (mac command status). mcs is cleared by the DS33Z11 when the operation is complete. reading from the mac registers requires the su.macra dh and su.macradl registers to be written with the address for the read operation. a read command is issued by writing a one to su.macrwc.mcrw and a zero to su.macrwc.mcs. su.macrwc.mcs is cleared by the ds 33z11 when the operation is complete. after mcs is clear, valid data is available in su.macrd0-su.macrd3. note that only one operation can be initiated (read or write) at one time. data cannot be written or read from the mac registers until the mcs bit has been cleared by the device. the mac registers are detailed in the following table.
DS33Z11 ethernet mapper 47 of 169 table 8-6 mac control registers address register register description 0000h-0003h su.maccr mac control register. this register is used for programming full duplex, half duplex, promiscuous mode, and back-off limit for half duplex. the transmit and receive enable bits must be set for the mac to operate. 0004h-0007h su.macah mac address high register. this provides the physical address for this mac. 0008h-000bh su.macal mac address low register. this provides the physical address for this mac. 0014h-0017h su.macmiia mii address register. the address for phy access through the mdio interface. 0018h-001bh su.macmiid mii data register. data to be written to (or read from) the phy through mdio interface. 001ch-001fh su.macfcr flow control register 0100h-0103h su.mmcctrl mmc control register bit 0 for resetting the status counters table 8-7 mac status registers address register register description 0200h-0203h su.rxfrmcntr all frames received counter 0204h-0207h su.rxfrmokctr number of received frames that are good 0300h-0303h su.txfrmctr number of frames transmitted 0308h-030bh su.txbytesctr number of bytes transmitted 030ch-030fh su.txbytesokctr number of bytes transmitted with good frames 0334h-0337h su.txfrmundr transmit fifo underflow counter 0338h-033bh su.txbdfrmsctr transmit number of frames aborted
DS33Z11 ethernet mapper 48 of 169 8.14.1 mii mode options the ethernet interface can be configured for mii operation by setting the hardware pin rmiimiis low. the mii interface consists of 17 pins. for instructions on clocking the ethernet interface while in mii mode, see section 8.3 . diagrams of system connections for mii operation are shown in figure 8-5 and figure 8-6 . 8.14.2 rmii mode the ethernet interface can be configured for rmii operat ion by setting the hardware pin rmiimiis high. rmii interface operates synchronously from the external 50 mhz reference (ref_clk). only 7 signals are required. the following figure shows the rmii architecture. note that dce mode is not supported for rmii mode and rmii is valid only for full duplex operation. figure 8-7 rmii interface txd[1:0] tx_en ref_clk rxd[1:0] crs_dv mac mii to rmii phy rmii to mii tx_en txd[3:0] tx_err tx_clk rx_crs rx_dv rx_crs rx_clk tx_en txd[3:0] tx_err tx_clk crs rx_dv rxd[3:0] rx_er rx_clk
DS33Z11 ethernet mapper 49 of 169 8.14.3 phy mii management block and mdio interface the mii management block allows for the host to control up to 32 phys, each with 32 registers. the mii block communicates with the external phy using 2-wire serial interface composed of mdc (serial clock) and mdio for data. the mdio data is valid on the rising edge of the mdc clock. the frame format for the mii management interface is shown figure 8-8 . the read/write control of the mii management is accomplished through the indirect su.macmiia mii management address register and data is passed through the indirect su.macmiid data register. these indirect registers are access ed through the mac control registers defined in table 8-6 . the mdc clock is internally generated and runs at 1.67 mhz. figure 8-8 mii management frame read 111...111 01 01 10 01 phya[4:0] phyr[4:0] zz 10 zzzzzzzzz z z preamble start opco de phy adrs phy reg turn aroun d data 111...111 phya[4:0] phyr[4:0] phyd[15:0] 32 bits 2 bits 2 bits 5 bits 5 bits 2 bits 16 bits idle 1 bit write
DS33Z11 ethernet mapper 50 of 169 8.15 bert the bert can be used for generation and detection of bert patterns. the bert is a software programmable test pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment. the following restrictions are related to the bert: the rden and tden are inputs that can be used to ?gap? bits. bert will transmit even when the device is set for x.86 mode and tden is configured as an output. the normal traffic flow is halted while the bert is in operation. if the bert is enabled for a serial port, it will override the normal connection. if there is a connection overridden by the bert, when bert operation is terminated the normal operation is restored. the transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data stream. the receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern payload for the programmable test pattern. bert features prbs and qrss patterns of 2 9 -1, 2 15 -1 2 23 -1 and qrss pattern support programmable repetitive pattern. the repetitive pattern length and pattern are programmable (length n = 1 to 32 and pattern = 0 to (2 n ? 1)). 24-bit error count and 32-bit bit count registers programmable bit error insertion. errors can be inserted individually 8.15.1 receive data interface 8.15.1.1 receive pattern detection the receive bert receives only the payload data and synchr onizes the receive pattern generator to the incoming pattern. the receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (lsb) or bit 1 to the most significant bit (msb) or bit 32. the i nput to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1), the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are individually programm able (1 to 32). the output of the receive pattern generator is the feedback. if qrss is enabled, the feedback is an xor of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. qrss is programmable (on or off). for prbs and qrss patterns, the feedback is forced to one if bits 1 through 31 are all zeros. depending on the type of pattern programmed, pattern detection performs either prbs synchronization or repetitive pattern synchronization. 8.15.1.2 prbs synchronization prbs synchronization synchronizes the receive pattern generator to the incoming prbs or qrss pattern. the receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least is incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern resynchronization is initiated. automatic pattern resynchronization can be disabled.
DS33Z11 ethernet mapper 51 of 169 figure 8-9 prbs synchronization state diagram sync load verify 1 bit error 32 bits loaded 3 2 b i t s w i t h o u t e r r o r s 6 o f 6 4 b i t s w i t h e r r o r s 8.15.2 repetitive pattern synchronization repetitive pattern synchronization synchronizes the receiv e pattern generator to the incoming repetitive pattern. the receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least sis incoming bits in the current 64-bit window do not match the receive prbs pattern generator, automatic pattern resynchronization is initiated. automatic pattern resynchronization can be disabled.
DS33Z11 ethernet mapper 52 of 169 figure 8-10 repetitive pattern synchronization state diagram sync match verify 1 bit error pattern matches 3 2 b i t s w i t h o u t e r r o r s 6 o f 6 4 b i t s w i t h e r r o r s 8.15.3 pattern monitoring pattern monitoring monitors the incoming data stream fo r out of synchronization (oos) condition, bit errors, and counts the incoming bits. an oos condition is declared when the synchronization state machine is not in the ?sync? state. an oos condition is terminated when the synchronization state machine is in the ?sync? state. bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. if they do not match, a bit error is declared, and the bit error and bit counts are incremented. if they match, only the bit count is incremented. the bit count and bit error count are not incremented when an oos condition exists. 8.15.4 pattern generation pattern generation generates the outgoing test pattern, and passes it onto error insertion. the transmit pattern generator is a 32-bit shift register that shifts data from the least significant bit (lsb) or bit 1 to the most significant bit (msb) or bit 32. the input to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1), the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are individually programmable. the output of the receive pattern generator is the feedback. if qrss is enabled, the feedback is an xor of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. qrss is programmable (on or off). for prbs and qrss patterns, the feedback is forced to one if bits 1 through 31 are all zeros. when a new pattern is loaded, the pattern generator is loaded with a pattern value before pattern generation starts. the pattern value is programmable (0 ? 2 n - 1). when prbs and qrss patterns are generated the seed value is all ones.
DS33Z11 ethernet mapper 53 of 169 8.15.4.1 error insertion error insertion inserts errors into the outgoing pattern data stream. errors are inserted one at a time single bit error insertion can be initiated from the microprocessor interface. if pattern inversion is enabled, the data stream is inverted before the overhead/stuff bits are inserted. pattern inversion is programmable (on or off). 8.15.4.2 performance monitoring update all counters stop counting at their maximum count. a counter register is updated by asserting (low to high transition) the performance monitoring update signal (pmu). during the counter register update process, the performance monitoring status signal (pms) is de-asserted. the counter register update process consists of loading the counter register with the current count, resetti ng the counter, forcing the zero count status indication low for one clock cycle, and then asserting pms. no events shall be missed during an update procedure. 8.16 transmit packet processor the transmit packet processor accepts data from the transmit fifo, performs bit reordering, fcs processing, packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. the data output from the transmit packet processor to the transmit serial interface is a serial data stream (bit synchronous mode). hdlc processing can be disabled (clear channel enable). disabling hdlc processing disables fcs processing, packet error insertion, stuffing, packet abort sequence insertion, and inter-frame padding. only bit reordering and packet scrambling are not disabled. bit reordering changes the bit order of each byte. if bi t reordering is disabled, the outgoing 8-bit data stream dt[1:8] with dt[1] being the msb and dt[8] being the lsb is output from the transmit fifo with the msb in tfd[7] (or 15, 23, or 31) and the lsb in tfd[0] (or 8, 16, or 24) of the transmit fifo data tfd[7:0] 15:8, 23:16, or 31:24). if bit reordering is enabled, the outgoing 8-bit data stream dt[1:8] is output from the transmit fifo with the msb in tfd[0] and the lsb in tfd[7] of the transmit fifo data tfd[7:0]. in bit synchronous mode, dt [1] is the first bit transmitted. bit reordering can be controlled by address pin a0 in hardware mode. fcs processing calculates an fcs and appends it to the packet. fcs calculat ion is a crc-16 or crc-32 calculation over the entire packet. the polynomial used for fcs-16 is x 16 + x 12 + x 5 + 1. the polynomial used for fcs-32 is x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1. the fcs is inverted after calculation. the fcs type is programmable. if fcs append is enabled, the calculated fcs is appended to the packet. if fcs append is disabled, the packet is transmitted without an fcs. the fcs append mode is programmable. if packet processing is disabled, fcs processing is not performed. packet error insertion inserts errors into the fcs bytes. a single fcs bit is corrupted in each errored packet. the fcs bit corrupted is changed from errored packet to errored packet. error insertion can be controlled by a register or by the manual error insertion input (li.tmei.tmei). t he error insertion initiation type (register or input) is programmable. if a register controls error insertion, the number and frequency of the errors are programmable. if fcs append is disabled, packet error insertion will not be performed. if packet processing is disabled, packet error insertion is not performed. stuffing inserts control data into the packet to prevent packet data from mimicking flags. a packet start indication is received, and stuffing is performed until, a packet end indica tion is received. bit stuffing consists of inserting a '0' directly following any five contiguous '1's. if packet processing is disabled, stuffing is not performed. there is at least one flag plus a programmable number of additional flags between packets. the inter-frame fill can be flags or all '1's followed by a start flag. if the inter-frame fill is all '1's, the number of '1's between the end and start flags does not need to be an integer number of bytes, however, there must be at least 15 consecutive '1's between the end and start flags. the inter-frame padding type is programmable. if packet processing is disabled, inter-frame padding is not performed. packet abort insertion inserts a packet abort sequences as necessary. if a packet abort indication is detected, a packet abort sequence is inserted and inter-frame padding is done until a packet start flag is detected. the abort sequence is ffh. if packet processing is disabled, packet abort insertion is not performed. the packet scrambler is a x 43 + 1 scrambler that scrambles the entire packet data stream. the packet scrambler runs continuously, and is never reset. in bit synchronous mode, scrambling is performed one bit at a time. in byte
DS33Z11 ethernet mapper 54 of 169 synchronous mode, scrambling is performed 8 bits at a time. packet scrambling is programmable. note in hardware mode, the scrambling is controlled by a1/sd. once all packet processing has been completed serial data stream is passed on to the transmit serial interface. 8.17 receive packet processor the receive packet processor accepts data from the receive serial interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, fcs error monitoring, fcs byte extraction, and bit reordering. the dat a coming from the receive serial interface is a serial data stream. packet processing can be disabled (clear channel enable). disabling packet processing disables packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, fcs error monitoring, and fcs byte extraction. only packet descrambling and bit reordering are not disabled. the packet descrambler is a self-synchronous x 43 + 1 descrambler that descrambles the entire packet data stream. packet descrambling is programmable. the descrambler runs continuously, and is never reset. the descrambling is performed one bit at a time. packet descrambling is programmable. if packet processing is disabled, the serial data stream is demultiplexed in to an 8-bit data stream before being passed on. note in hardware mode, the scrambling is controlled by a1/sd. if packet processing is disabled, a packet boundary is arbitrarily chosen and the data is divided into "packets" of programmable size (dependent on maximum packet size setting). these packets are then passed on to bit reordering with packet start and packet end indications. data then bypasses packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, fcs error monitoring, and fcs byte extraction. packet delineation determines the packet boundary by identifying a packet start or end flag. each time slot is checked for a flag sequence (7eh). once a flag is found, it is identified as a start/end flag and the packet boundary is set. the flag check is performed one bit at a time. if packet processing is disabled, packet delineation is not performed. inter-frame fill filtering removes the inter-frame fill between packets. when a packet end flag is detected, all data is discarded until a packet start flag is detected. the inter-frame fill can be flags or all '1's. the number of '1's between flags does not need to be an integer number of bytes, and if at least 7 '1's are detected in the first 16 bits after a flag, all data after the flag is discarded until a start flag is detected. there may be only one flag between packets. when the inter-frame fill is flags, the flags may have a shared zero (011111101111110). if there is less than 16 bits between two flags, the data is discarded. if packet processing is disabled, inter-frame fill filtering is not performed. packet abort detection searches for a packet abort sequence. between a packet start flag and a packet end flag, if an abort sequence is detected, the packet is marked with an abort indication, the aborted packet count is incremented, and all subsequent data is discarded until a packet start flag is detected. the abort sequence is seven consecutive ones. if packet processing is disabled, packet abort detection is not performed. destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence. a start flag is detected, a packet start is set, the flag is discarded, destuffing is performed until an end flag is detected, a packet end is set, and the flag is discarded. in bit synchronous mode, bit destuffing is performed. bit destuffing consists of discarding any '0' that directly follows five contiguous '1's. after destuffing is completed, the serial bit stream is demultiplexed into an 8-bit parallel data stream and passed on with packet start, packet end, and packet abort indications. if there is less than eight bits in the last byte, an invalid packet flag is raised, the packet is tagged with an abort indication, and the packet size violation c ount is incremented. if packet processing is disabled, destuffing is not performed. packet size checking checks each packet for a programmable maximum and programmable minimum size. as the packet data comes in, the total number of bytes is counted. if the packet length is below the minimum size limit, the packet is marked with an aborted indication, and t he packet size violation count is incremented. if the packet length is above the maximum size limit, the packet is marked with an aborted indication, the packet size violation count is incremented, and all packet data is discarded until a packet start is received. the minimum and maximum lengths include the fcs bytes, and are determined after destuffing has occurred. if packet processing is disabled, packet size checking is not performed. fcs error monitoring checks the fcs and aborts errored packets. if an fcs error is detected, the fcs errored packet count is incremented and the packet is marked with an aborted indication. if an fcs error is not detected,
DS33Z11 ethernet mapper 55 of 169 the receive packet count is incremented. the fcs type (16-bit or 32-bit) is programmable. if fcs processing or packet processing is disabled, fcs error monitoring is not performed. fcs byte extraction discards the fcs bytes. if fcs extraction is enabled, the fcs bytes are extracted from the packet and discarded. if fcs extraction is disabled, the fcs bytes are stored in the receive fifo with the packet. if fcs processing or packet processing is disabled, fcs byte extraction is not performed. bit reordering changes the bit order of each byte. if bit reordering is disabled, the incoming 8-bit data stream dt[1:8] with dt[1] being the msb and dt[8] being the lsb is output to the receive fifo with the msb in rfd[7] (or 15, 23, or 31) and the lsb in rfd[0] (or 8, 16, or 24) of the receive fifo data rfd[7:0] (or 15:8, 23:16, or 31:24). if bit reordering is enabled, the incoming 8-bit data stream dt[1:8] is output to the receive fifo with the msb in rfd[0] and the lsb in rfd[7] of the receive fifo data rfd[7:0]. dt[1] is the first bit received from the incoming data stream. bit reordering can be controlled by pin a0 in hardware mode. once all of the packet processing has been completed, the 8-bit parallel data stream is demultiplexed into a 32-bit parallel data stream. the receive fifo data is passed on to the receive fifo with packet start, packet end, packet abort, and modulus indications. at a packet end, the 32- bit word may contain 1, 2, 3, or 4 bytes of data depending on the number of bytes in the packet. the modulus i ndications indicate the number of bytes in the last data word of the packet.
DS33Z11 ethernet mapper 56 of 169 8.18 x.86 encoding and decoding x.86 protocol provides a method for encapsulating ether net frame onto laps. laps provides hdlc type framing structure for encapsulation of ethernet frames. laps encapsulated frames can be used to send data onto a sonet/sdh network. the DS33Z11 expects a byte synchr onization signal to provide the byte boundary for the x.86 receiver. this is provided by the rbsy nc pin. the functional timing is shown in figure 10-4 . the x.86 transmitter provides a byte boundary indicator with t he signal tbsync. the functional timing is shown in figure 10-3 . figure 8-11 laps encoding of mac frames concept ieee 802.3 mac frame laps rate adaption sdh
DS33Z11 ethernet mapper 57 of 169 figure 8-12 x.86 encapsulation of the mac field flag(0x7e) address(0x04) control(0x03) 1st octect of sapi(0xfe) 2nd octect of sapi(0x01) destination adrs(da) source adrs(sa) length/type number of bytes 1 1 1 1 1 6 6 2 mac client data 46-1500 pad fcs for mac 4 fcs for laps flag(0x7e) 4 msb lsb the DS33Z11 will encode the mac frame with the laps encapsulation on a complete serial stream if configured for x.86 mode in the register li.tx86e. the DS33Z11 provides the following functions: control registers for address, sapi, destination address, source address 32 bit fcs enabled programmable x 43 +1 scrambling the sequence of processing performed by the receiver is as follows: programmable octets x 43 +1 descrambling detect the start flag (7e) remove rate adaptation octets 7d, dd. perform transparency-processing 7d, 5e is converted to 7e and 7d, 5d is converted to 7d. check for a valid address, control and sapi fields (li.trx86a to li.trx86sapil) perform fcs checking detect the closing flag.
DS33Z11 ethernet mapper 58 of 169 the x86 received frame is aborted if: if 7d,7e is detected. this is an abort packet sequence in x.86 invalid fcs is detected the received frame has less than 6 octets control, sapi and address field are mismatched to the programmed value octet 7d and octet other than 5d, 5e, 7e, or dd is detected for the transmitter if x.86 is enabled the sequence of processing is as follows: construct frame including start flag sapi, control and mac frame calculate fcs perform transparency processing - 7e is translated to 7d5e, 7d is translated to 7d5d append the end flag(7e) scramble the sequence x 43 +1 note that the serial transmit and receive registers apply to the x.86 implementations with specific exceptions. the exceptions are outlined in the serial interface transmit and receive register sections.
DS33Z11 ethernet mapper 59 of 169 8.19 committed informati on rate controller the DS33Z11 provides a cir provisioning facility. the cir can be used restricts the transport of received mac data to a programmable rate. this is shown in figure 8-13 . the cir will restrict the data flow from the receive mac to transmit hdlc. this can be used for provisioning and billing functions towards the wan. the user must set the cir register to control the amount of data throughput from the mac to hdlc transmit. the cir register is in granularity of 500 kbps with a range of 0 to 52 mbps. the operation of the cir is as follows: the cir block counts the credits that are accumulated at the end of every 125 ms if data is received and stored in the sdram to be sent to the serial interface, the interface will request the data if there is a positive credit balance. if the credit balance is negative, transmit interface does not request data new credit balance is calculated credit balance = old credi t balance ? frame size in bytes after the frame is sent the credit balance is incremented every 125 milliseconds by cir/8 credit balances not used in 250 milliseconds are reset to 0 the maximum value of cir can not exceed the transmit line rate if the data rate received from the ethernet interface is higher than the cir, the receive queue buffers will fill and the high threshold watermark will invoke flow control to reduce the incoming traffic rate. the cir function is only available for software mode of operation only cir function is only available in data received at the ethernet interface to be sent to wan. there is not cir functionality for data arriving from the wan to be sent to the ethernet interface negative credits are not allowed, if there is not a credit balance, no frames are sent until there is a credit balance again.
DS33Z11 ethernet mapper 60 of 169 figure 8-13 cir in the wan transmit path mac rmii mii sdram interface buffer dev div by 2,4,12 output clocks 25,50 mhz 100 mhz oscillator sysclki sdclko eprom spi_sclk (max 8.33mhz) buffer dev div by 1,2,4,10 output clocks: 50,25 mhz,2.5 mhz 50 or 25 mhz oscillator tx_clk1 rx_clk1 tclki1 rclki1 ref_clko 50 or 25 mhz mdc ref_clki sdram hdlc + serial interface cir line 1 arbiter x.86 tser rser rxd txd
DS33Z11 ethernet mapper 61 of 169 8.20 hardware mode the hardware mode settings are provided for users who do not want to utilize a microprocessor or eeprom. the hardware mode default queue sizes and watermark thresholds can be selected for various line rates using the modec pins. the user can control the dte/dce, rmii/mii and half duplex/full duplex and setting with hardware pins dcedtes, rmiimiis, and fullds selection. the flow control (pause and back pressure) can be configured with the afcs hardware pins. the user can also cont rol bit order, data scrambling, and x.86 encapsulation using the a0, a1, and a2 pins respectively. note that in the 100-pin csbga package option (ds33zh11), three pins are reserved for these three signals in future package revisions, but may not be included in the current version. contact the factory at telecom.support@dalsemi.com for more details. the DS33Z11 has 3 different default hardware settings. this is outlined in the following tables. the typical applications for each of the hardware modes are outlined in following tables. note that in the hardware only mode the following restrictions apply: the ports are powered up and ready to transmit/receive after reset bert functionality is not supported in hardware mode. queue size and watermarks are fixed receive and transmit hdlc fcs are 16 bits transmit packets are resent if errors occur, receive packets are rejected if errors occur mii, rmii, full and half duplex, automatic flow control, dte, dce, 100 or 10 mbps can be selected through hardware pins tden and rden are not supported and should be tied high cir function is not supported in hardware mode. table 8-8 hardware mode and typical applications modec pin settings applications 00 serial interface connected to a t1/e1 line, ethernet interface set to 10 mbps or 100 mbps m ii/rmii. transmitter and receiver are enabled for communication. 10 serial interface connected to a t3/e3 line, ethernet interface set to 10 mbps or 100 mbps m ii/rmii. transmitter and receiver are enabled for communication. the specific registers and detailed functions for each of the hardware modes are detailed in the following tables.
DS33Z11 ethernet mapper 62 of 169 table 8-9 specific functional defa ult values for hardware mode functional block register reference default value in hardware mode description global connection between serial and ethernet interfaces gl.con1 0000 0001b connection established for serial 1 to ethernet 1. serial data transmit serial interface configuration li.tslcr 0000 0000b transmit data enable is not supported and should be tied high. the user must provide gapped clo cks to mask bits if needed. the tr ansmit serial data will output on the rising edge of tclki1-4. serial interface reset and power-down li.rstpd 0000 0000b in default hardware mode the serial interface transmitter is powered up and ready to go. transmit fcs li.tppcl 0001 0000b* fcs is set to 16 bits for the hdlc transmitter. transmit inter frame gap li.tifgc 0000 0001b transmit inter frame gap is one byte. the value is 7e. receive fcs li.rppcl 0001 0000b* receive hdlc fcs is set to 16 bits. receive scrambling and bit ordering controlled by hardware pins receive maximum packet length li.rmpsc 2016 bytes the receive maximum packet length is set to 2016 bytes not including the hdlc fcs. any packets greater than 2016 bytes are rejected. receive serial port configuration li.rslcr 0000 0000b receive rden enable will not be supported and should be tied high. the received data is sampled on the falling edge and gapped clock is supported. transmit packet resend criteria su.tfrc 0000 0000b any error: jabber timeout, loss of carrier, excessive deferral, late collision, excessive collisions, under run, collision, def erred, heartbeat fail will result in resending of packets receive packet rejection control su.rfrc 0000 0000b broadcast frames, control frames, and errored packets are rejected. receiver maximum size su.rmfsr 0111 1110b the maximum receiver packet size is 2016 bytes including the mac fcs. any packet larger that 2016 is rejected ethernet mac control register su.maccr 0000 0000 0000 0100 0000 0000 0000 1100b* duplex mode(bit 20) is determined by the fullds pin (msb to lsb) mac flow control register su.macfcr 0000 0001 0100 0000 0000 0000 0000 0000b* flow control is determined by the afcs pin. pause timer = 320 (140h) slots (msb to lsb)
DS33Z11 ethernet mapper 63 of 169 functional block register reference default value in hardware mode description queue size and thresholds transmit queue size ar.tqsc1 ar.tqsc1 0001 0100b 0001 1000b 640 packets, modec[1:0] = 00 768 packets, modec[1:0] = 10 transmit queue high threshold li.tqht li.tqht 0000 1100b 0000 1100b 384 packets, modec[1:0] = 00 384 packets, modec[1:0] = 01 transmit queue low threshold li.tqlt li.tqlt 0000 0110b 0000 0110b 192 packets*, modec[1:0] = 00 192 packets*, modec[1:0] = 10 receive queue size ar.rqsc1 ar.rqsc1 0010 1100b 0010 1000b 1408 packets*, modec[1:0] = 00 1280 packets*, modec[1:0] = 10 receive queue low threshold su.rqlt su.rqlt 0000 1111b 0000 1100b 480 packets*, modec[1:0] = 00 384 packets*, modec[1:0] = 10 receive queue high threshold su.rqht su.rqht 0001 1110b 0001 1000b 960 packets*, modec[1:0] = 00 768 packets*, modec[1:0] = 10 * the default values for these registers are different than in the software mode. note: each ?packet? above is 2048 bytes.
DS33Z11 ethernet mapper 64 of 169 table 8-10 hardware mode pins pin hardware mode function hwmode 0 = hardware mode disabled. 1 = hardware mode enabled. modec[1:0] select the hardware mode default settings. rmiimiis 0 = mii operation. 1 = rmii operation. dcedtes 1 = dce operation 0 = dte operation fullds 0 = half duplex mode. 1 = full duplex mode. a2/x86ed 0 = x.86 mode is disabled. 1 = x.86 mode is enabled for transmit and receive. a1/scd 0 = x 43 +1 scrambling/descrambling is enabled. 1 = x 43 +1 scrambling/descrambling is disabled. a0/breo 0 = hdlc transmit and receive bits are normal. the msb is transmitted and received first. 1 = hdlc transmit and receive bits are reversed. the lsb is transmitted and received first.
DS33Z11 ethernet mapper 65 of 169 9 device registers ten address lines are used to address the register space. table 9-1 shows the register map for the DS33Z11 is shown in. the addressable range for the device is 0000h to 08ffh. each register section is 64 bytes deep. global registers are preserved for software compatibility with mult iport devices. the serial interface (line) registers are used to configure the serial port and the associated transport protocol. the ethernet interface (subscriber) registers are used to control and observe each of the ethernet ports. the registers associated with the mac must be configured through indirect register write /read access due to the architecture of the device. when writing to a register input va lues for unused bits and r egisters (those designated wi th ?-?) should be zero, as these bits and registers are reserved. when a register is read from, the values of the unused bits and registers should be ignored. a latched status bit is set when an event happens and is cleared when read. the register details are provided in the following tables. table 9-1 register address map global registers arbiter bert serial interface ethernet interface 0000h ? 003fh 0040h ? 007fh 0080h ? 00bfh - - port 1 - - - 00c0h ? 013fh 0140h ? 017fh unused address space: 180h - 7ffh
DS33Z11 ethernet mapper 66 of 169 9.1 register bit maps table 9-2 , table 9-3 , table 9-4 , table 9-5 , table 9-6 , and table 9-7 contain the registers of the DS33Z11. bits that are reserved are noted with a single dash ?-?. all regi sters not listed are reserved and should be initialized with a value of 00h for proper operation, unless otherwise noted. 9.1.1 global register bit map table 9-2 global register bit map a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 00h gl.idrl id07 id06 id05 id04 id03 id02 id01 id00 01h gl.idrh id15 id14 id13 id12 id11 id10 id09 id08 02h gl.cr1 - - - - - ref_clko intm rst 03h gl.blr - - - - - - - gl.blc1 04h gl.rtcal - - - rlcals1 - - - tlcals1 05h gl.srcals - - - - - - refclks syscls 06h gl.lie - - - lin1tie - - - lin1rie 07h gl.lis - - - lin1tis - - - lin1ris 08h gl.sie - - - - - - - sub1ie 09h gl.sis - - - - - - - sub1is 0ah gl.trqie - - - tq1ie - - - rq1ie 0bh gl.trqis - - - tq1is - - - rq1is 0ch gl.bie - - - - - - - bie 0dh gl.bis - - - - - - - bis 0eh gl.con1 - - - - - - - line0 0fh reserved - - - - - - - - 10h reserved - - - - - - - - 11h reserved - - - - - - - - 12h gl.c1qpr - - - - c1mrprr c1hwprr c1mhpr c1hrpr 13h reserved - - - - - - - - 14h reserved - - - - - - - - 15h reserved - - - - - - - - 20h gl.bisten - - - - - - - biste 21h gl.bistpf - - - - - - bistdn bistpf 22h - 3fh are reserved.
DS33Z11 ethernet mapper 67 of 169 9.1.2 arbiter register bit map table 9-3 arbiter register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 40h ar.rqsc1 rqsc7 rqsc6 rqsc5 rqsc4 rqsc3 rqsc2 rqsc1 rqsc0 41h ar.tqsc1 tqsc7 tqsc6 tqsc5 tqsc4 tqsc3 tqsc2 tqsc1 tqsc0 9.1.3 bert register bit map table 9-4 bert register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 080h bcr - pmu rnpl rpic mpr aprd tnpl tpic 081h reserved - - - - - - - - 082h bpclr - qrss pts plf4 plf3 plf2 plf1 plf0 083h bpchr - - - ptf4 ptf3 ptf2 ptf1 ptf0 084h bspb0r bsp7 bsp6 bsp5 bsp4 bsp3 bsp2 bsp1 bsp0 085h bspb1r bsp15 bsp14 bsp13 bsp12 bsp11 bsp10 bsp9 bsp8 086h bspb2r bsp23 bsp22 bsp21 bsp20 bsp19 bsp18 bsp17 bsp16 087h bspb3r bsp31 bsp30 bsp29 bsp28 bsp27 bsp26 bsp25 bsp24 088h teicr - - tier2 tier1 ti er0 bei tsei - 08ah reserved - - - - - - - - 08bh reserved - - - - - - - - 08ch bsr - - - - pms - bec oos 08dh reserved - - - - - - - - 08eh bsrl - - - - pmsl bel becl oosl 08fh reserved - - - - - - - - 90h bsrie - - - - pmsie beie becie oosie 91h reserved - - - - - - - - 92h reserved - - - - - - - - 93h reserved - - - - - - - - 94h rbecb0r bec7 bec6 bec5 bec4 bec3 bec2 bec1 bec0 95h rbecb1r bec15 bec14 bec13 bec12 bec11 bec10 bec9 bec8 96h rbecb2r bec23 bec22 bec21 bec20 bec19 bec18 bec17 bec16 97h reserved - - - - - - - - 98h rbcb0 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 99h rbcb1 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 9ah rbcb2 bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 9bh rbcb3 bc31 bc30 bc29 bc28 bc27 bc26 bc25 bc24 9ch reserved - - - - - - - - 9dh reserved - - - - - - - - 9eh reserved - - - - - - - - 9fh reserved - - - - - - - -
DS33Z11 ethernet mapper 68 of 169 9.1.4 serial interface register bit map table 9-5 serial interface register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 0c0h li.tslcr - - - - - - - tdenplt 0c1h li.rstpd - - - - - - reset - 0c2h li.lpbk - - - - - - - qlp 0c3h reserved - - - - - - - - 0c4h li.tppcl - - tfad tf16 tifv tsd tbre - 0c5h li.tifgc tifg7 tifg6 tifg5 tifg4 tifg3 tifg2 tifg1 tifg0 0c6h li.teplc tpen7 tpen6 tpen5 tpen4 tpen3 tpen2 tpen1 tpen0 0c7h li.tephc meims tper6 tper5 tper4 tper3 tper2 tper1 tper0 0c8h li.tppsr - - - - - - - tepf 0c9h li.tppsrl - - - - - - - tepfl 0cah li.tppsrie - - - - - - - tepfie 0cbh reserved - - - - - - - - 0cch li.tpcr0 tpc7 tpc6 tpc5 tpc4 tpc3 tpc2 tpc1 tpc0 0cdh li.tpcr1 tpc15 tpc14 tpc13 tpc12 tpc11 tpc10 tpc9 tpc8 0ceh li.tpcr2 tpc23 tpc22 tpc21 tpc20 tpc19 tpc18 tpc17 tpc16 0cfh reserved - - - - - - - - 0d0h li.tbcr0 tbc7 tbc6 tbc5 tbc4 tbc3 tbc2 tbc1 tbc0 0d1h li.tbcr1 tbc15 tbc14 tbc13 tbc12 tbc11 tbc10 tbc9 tbc8 0d2h li.tbcr2 tbc23 tbc22 tbc21 tbc20 tbc19 tbc18 tbc17 tbc16 0d3h li.tbcr3 tbc31 tbc30 tbc29 tbc28 tbc27 tbc26 tbc25 tbc24 0d4h li.tmei - - - - - - - tmei 0d5h reserved - - - - - - - - 0d6h li.thpmuu - - - - - - - tpmuu 0d7h li.thpmus - - - - - - - tpmus 0d8h li.tx86ede - - - - - - - x86ed 0d9h li.trx86a x86tra7 x86tra6 x86tra5 x86tra4 x86tra3 x86tra2 x86tra1 x86tra0 0dah li.trx8c x86trc7 x86trc6 x86trc5 x86trc4 x86trc3 x86t rc2 x86trc1 x86trc0 0dbh li.trx86sapih trsapih7 trsapih6 trsapih5 trsapih4 trsapih3 trsapi h2 trsapih1 trsapih0 0dch li.trx86sapil trsapil7 trsapil6 trsapi l5 trsapil4 trsapil3 tr sapil2 trsapil1 trsapil0 0ddh li.cir cire cir6 cir5 cir4 cir3 cir2 cir1 cir0 100h li.rslcr - - - - - - - rdenplt 101h li.rppcl - - rfpd rf16 rfed rdd rbre rcce 102h li.rmpscl rmx7 rmx6 rmx5 rmx4 rmx3 rmx2 rmx1 rmx0 103h li.rmpsch rmx15 rmx14 rmx13 rmx12 rmx11 rmx10 rmx9 rmx8 104h li.rppsr - - - - - repc rapc rspc 105h li.rppsrl repl rapl ripdl rspdl rlpdl repcl rapcl rspcl 106h li.rppsrie repie rapie ripdie rspdie rlpdie repcie rapcie rspcie 107h reserved 108h li.rpcb0 rpc7 rpc6 rpc5 rpc4 rpc3 rpc2 rpc1 rpc0 109h li.rpcb1 rpc15 rpc14 rpc13 rpc12 rpc11 rpc10 rpc09 rpc08 10ah li.rpcb2 rpc23 rpc22 rpc21 rpc20 rpc19 rpc18 rpc17 rpc16 10ch li.rfpcb0 rfpc7 rfpc6 rfpc5 rfpc4 rfpc3 rfpc2 rfpc1 rfpc0 10dh li.rfpcb1 rfpc15 rfpc14 rfpc13 rfpc12 rfpc11 rfpc10 rfpc9 rfpc8 10eh li.rfpcb2 rfpc23 rfpc22 rfpc21 rfpc20 rfpc19 rfpc18 rfpc17 rfpc16 10fh reserved 110h li.rapcb0 rapc7 rapc6 rapc5 rapc4 rapc3 rapc2 rapc1 rapc0 111h li.rapcb1 rapc15 rapc14 rapc13 rapc12 rapc11 rapc10 rapc9 rapc8 112h li.rapcb2 rapc23 rapc22 rapc21 rapc20 rapc19 rapc18 rapc17 rapc16
DS33Z11 ethernet mapper 69 of 169 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 113h reserved - - - - - - - - 114h li.rspcb0 rspc7 rspc6 rspc5 rspc4 rspc3 rspc2 rspc1 rspc0 115h li.rspcb1 rspc15 rspc14 rspc13 rspc12 rspc11 rspc10 rspc9 rspc8 116h li.rspcb2 rspc23 rspc22 rspc21 rspc20 rspc19 rspc18 rspc17 rspc16 118h li.rbc0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 119h li.rbc1 rbc15 rbc14 rbc13 rbc12 rbc11 rbc10 rbc9 rbc8 11ah li.rbc2 rbc23 rbc22 rbc21 rbc20 rbc19 rbc18 rbc17 rbc16 11bh li.rbc3 rbc31 rbc30 rbc29 rbc28 rbc27 rbc26 rbc25 rbc24 11ch li.rac0 rebc7 rebc6 rebc5 rebc4 rebc3 rebc2 rebc1 rebc0 11dh li.rac1 rebc15 rebc14 rebc13 rebc12 rebc11 rebc10 rebc9 rebc8 11eh li.rac2 rebc23 rebc22 rebc21 rebc20 rebc19 rebc18 rebc17 rebc16 11fh li.rac3 rebc31 rebc30 rebc29 rebc28 rebc27 rebc26 rebc25 rebc24 120h li.rhpmuu - - - - - - - rpmuu 121h li.rhpmus - - - - - - - rpmuus 122h li.rx86s - - - - sapihne sapilne cne ane 123h li.rx86lsie - - - - sapine01im sapinefeim cne3lim ane4im 124h li.tqlt tqlt7 tqlt6 tqlt 5 tqlt4 tqlt3 t qlt2 tqlt1 tqlt0 125h li.tqht tqht7 tqht6 tqht5 tqht4 tqht3 tqht2 tqht1 tqht0 126h li.tqtie - - - - tfovfie tqovfie tqhtie tqltie 127h li.tqctls - - - - tfovfls tqovfls tqhtls tqltls 0deh ? 0ffh, 128h ? 13fh are reserved.
DS33Z11 ethernet mapper 70 of 169 9.1.5 ethernet interface register bit map table 9-6 ethernet interface register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 140h su.macradl macra7 macra6 macra5 macra4 macra3 macra2 macra1 macra0 141h su.macradh macra15 macra14 macra13 macra12 macra11 macra10 macra09 macra08 142h su.macrd0 macrd7 macrd6 macrd5 macrd4 macrd3 macrd2 macrd1 macrd0 143h su.macrd1 macrd15 macrd14 macrd13 macrd12 macrd11 macrd10 macrd9 macrd8 144h su.macrd2 macrd23 macrd22 macrd21 macrd20 macrd19 macrd18 macrd17 macrd16 145h su.macrd3 macrd31 macrd30 macrd29 macrd28 macrd27 macrd26 macrd25 macrd24 146h su.macwd0 macwd7 macwd6 macwd5 macwd4 macwd3 macwd2 macwd1 macwd0 147h su.macwd1 macwd15 macwd14 macwd13 macwd12 macwd11 macwd10 macwd09 macwd08 148h su.macwd2 macwd23 macwd22 macwd21 macwd20 macwd19 macwd18 macwd17 macwd16 149h su.macwd3 macd31 macd30 macd29 macd28 macd27 macd26 macd25 macd24 14ah su.macawl macaw 7 macaw 6 macaw 5 macaw4 macaw3 macaw2 macaw1 macaw0 14bh su.macawh macaw 15 macaw 14 macaw 13 macaw12 macaw11 macaw10 macaw9 macaw8 14ch su.macrwc - - - - - - mcrw mcs 14eh reserved - - - - - - - - 14fh su.lpbk - - - - - - - qlp 150h su.gcr - - - - crcs h10s atflow jame 151h su.tfrc - - - - ncfq tpdfcb tprhbc tprcb 152h su.tfsl ur ec lc ed loc noc - fabort 153h su.tfsh pr hbf cc3 cc2 cc1 cc0 lco def 154h su.rfsb0 fl7 fl6 fl5 fl4 fl3 fl2 fl1 fl0 155h su.rfsb1 rf wt fl13 fl12 fl11 fl10 fl9 fl8 156h su.rfsb2 - - crce db miie ft cs ftl 157h su.rfsb3 mf - - bf mcf uf cf le 158h su.rmfsrl rmps7 rmps6 rmps5 rmps4 rmps3 rmps2 rmps1 rmps0 159h su.rmfsrh rmps15 rmps14 rmps13 rmps12 rmps11 rmps10 rmps09 rmps08 15ah su.rqlt rqlt7 rqlt6 rqlt5 rqlt4 rqlt3 rqlt2 rqlt1 rqlt0 15bh su.rqht rqht7 rqht6 rqht5 rqht4 rqht3 rqht2 rqht1 rqht0 15ch su.qrie - - - - rfovfie rqvfie rqltie rqhtie 15dh su.qcrls - - - - rfovfls rqovfls rqhtls rqltls 15eh su.rfrc - ucfr cfrr lerr crcerr dbr miier bfr 15fh ? 17fh are reserved.
DS33Z11 ethernet mapper 71 of 169 9.1.6 mac register bit map table 9-7 mac indirect register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 0000h su.maccr 31:24 reserved reserved reserved hdb ps reserved reserved reserved 0001h 23:16 dro oml1 oml0 f reserved reserved reserved reserved 0002h 15:8 reserved reserved reserved lcc reserved drty reserved astp 0003h 7:0 bolmt1 bolmt0 dc reserved te re reserved reserved 0004h su.macah 31:24 reserved reserved reserved reserved reserved reserved reserved reserved 0005h 23:16 reserved reserved reserved reserved reserved reserved reserved reserved 0006h 15:8 padr47 padr46 padr45 padr44 padr43 padr42 padr41 padr40 0007h 7:0 padr39 padr38 padr37 padr36 padr35 padr34 padr33 padr32 0008h su.macal 31:24 padr31 padr30 padr29 padr28 padr27 padr26 padr25 padr24 0009h 23:16 padr23 padr22 padr21 padr20 padr19 padr18 padr17 padr16 000ah 15:8 padr15 padr14 padr13 padr12 padr11 padr10 padr09 padr08 000bh 7:0 padr07 padr06 padr05 padr04 padr03 padr02 padr01 padr00 000ch reserved reserved reserved reserved reserved reserved reserved reserved reserved 000dh reserved reserved reserved reserved reserved reserved reserved reserved reserved 000eh reserved reserved reserved reserved reserved reserved reserved reserved reserved 000fh reserved reserved reserved reserved reserved reserved reserved reserved reserved 0010h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0011h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0012h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0013h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0014h su.macmiia 31:24 reserved reserved reserved reserved reserved reserved reserved reserved 0015h 23:16 reserved reserved reserved reserved reserved reserved reserved reserved 0016h 15:8 phya4 phya3 phya2 phya1 phya0 miia4 miia3 miia2 0017h 7:0 miia1 miia0 reserved reserved reserved reserved miiw miib 0018h su.macmiid 31:24 reserved reserved reserved reserved reserved reserved reserved reserved 0019h 23:16 reserved reserved reserved reserved reserved reserved reserved reserved 001ah 15:8 miid15 miid14 miid13 miid12 miid11 miid10 miid09 miid08 001bh 7:0 miid07 miid06 miid05 miid04 miid03 miid02 miid01 miid00 001ch su.macfcr 31:24 pt15 pt14 pt13 pt12 pt11 pt10 pt09 pt08 001dh 23:16 pt07 pt06 pt05 pt04 pt03 pt02 pt01 pt00 001eh 15:8 reserved reserved reserved reserved reserved reserved reserved reserved 001fh 7:0 reserved reserved reserved reserved reserved pcf fce fcb 100h su.mmcctrl 31:24 reserved reserved reserved reserved reserved reserved reserved reserved 101h 23:16 reserved reserved reserved reserved reserved reserved reserved reserved 102h 15:8 reserved reserved mxfrm10 mxfrm9 mxfrm8 mxfrm7 mxfrm6 mxfrm5 103h 7:0 mxfrm4 mxfrm3 mxfrm2 mxfrm1 mxfrm0 reserved reserved reserved 10ch reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 10dh reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 10eh reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 10fh reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved
DS33Z11 ethernet mapper 72 of 169 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 110h reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 111h reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 112h reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 113h reserved ? initialize to ff reserved reserved reserved reserved reserved reserved reserved reserved 200h su.rxfrmctr 31:24 rxfrmc31 rxfrmc30 rxfrmc29 rxfrmc28 rxfrmc27 rxfrmc26 rxfrmc25 rxfrmc24 201h 23:16 rxfrmc23 rxfrmc22 rxfrmc21 rxfrmc20 rxfrmc19 rxfrmc18 rxfrmc17 rxfrmc16 202h 15:8 rxfrmc15 rxfrmc14 rxfrmc13 rxfrmc12 rxfrmc11 rxfrmc10 rxfrmc9 rxfrmc8 203h 7:0 rxfrmc7 rxfrmc6 rxfrmc5 rxfrmc4 rxfrmc3 rxfrmc2 rxfrmc1 rxfrmc0 204h su.rxfrmokctr 31:24 rxfrmok31 rxfrmok30 rxfrmok29 rxfrmok28 rxfrmok27 rxfrmok26 rxfrmok25 rxfrmok24 205h 23:16 rxfrmok23 rxfrmok22 rxfrmok21 rxfrmok20 rxfrmok19 rxfrmok18 rxfrmok17 rxfrmok16 206h 15:8 rxfrmok15 rxfrmok14 rxfrmok13 rxfrmok12 rxfrmok11 rxfrmok10 rxfrmok9 rxfrmok8 207h 7:0 rxfrmok7 rxfrmok6 rxfrmok5 rxfrmok4 rxfrmok3 rxfrmok2 rxfrmok1 rxfrmok0 300h su.txfrmctr txfrmc31 txfrmc30 txfrmc29 txfrmc28 txfrmc27 txfrmc26 txfrmc25 txfrmc24 301h 23:16 txfrmc23 txfrmc22 txfrmc21 txfrmc20 txfrmc19 txfrmc18 txfrmc17 txfrmc16 302h 15:8 txfrmc15 txfrmc14 txfrmc13 txfrmc12 txfrmc11 txfrmc10 txfrmc9 txfrmc8 303h 7:0 txfrmc7 txfrmc6 txfrmc5 txfrmc4 txfrmc3 txfrmc2 txfrmc1 txfrmc0 308h su.txbytesctr txbytec31 txbytec30 txbytec29 txbytec28 txbytec27 txbytec26 txbytec25 txbytec24 309h 23:16 txbytec23 txbytec22 txbytec21 txbytec20 txbytec19 txbytec18 txbytec17 txbytec16 30ah 15:8 txbytec15 txbytec14 txbytec13 txbytec12 txbytec11 txbytec10 txbytec9 txbytec8 30bh 7:0 txbytec7 txbytec6 txbytec5 txbytec4 txbytec3 txbytec2 txbytec1 txbytec0 30ch su.txbytesokctr txbyteok31 txbyteok30 txbyteok29 txbyteok28 txbyteok27 txbyteok26 txbyteok25 txbyteok24 30dh 23:16 txbyteok23 txbyteok22 txbyteok21 txbyteok20 txbyteok19 txbyteok18 txbyteok17 txbyteok16 30eh 15:8 txbyteok15 txbyteok14 txbyteok13 txbyteok12 txbyteok11 txbyteok10 txbyteok9 txbyteok8 30fh 7:0 txbyteok7 txbyteok6 txbyteok5 txbyteok4 txbyteok3 txbyteok2 txbyteok1 txbyteok0 334h su.txfrmundr txfrmu31 txfrmu30 txfrmu29 txfrmu28 txfrmu27 txfrmu26 txfrmu25 txfrmu24 335h 23:16 txfrmu23 txfrmu22 txfrmu21 txfrmu20 txfrmu19 txfrmu18 txfrmu17 txfrmu16 336h 15:8 txfrmu15 txfrmu14 txfrmu13 txfrmu12 txfrmu11 txfrmu10 txfrmu9 txfrmu8 337h 7:0 txfrmu7 txfrmu6 txfrmu5 txfrmu4 txfrmu3 txfrmu2 txfrmu1 txfrmu0 338h su.txbdfrmctr txfrmbd31 txfrmbd30 txfrmbd29 txfrmbd28 txfrmbd27 txfrmbd26 txfrmbd25 txfrmbd24 339h 23:16 txfrmbd23 txfrmbd22 txfrmbd21 txfrmbd20 txfrmbd19 txfrmbd18 txfrmbd17 txfrmbd16 33ah 15:8 txfrmbd15 txfrmbd14 txfrmbd13 txfrmbd12 txfrmbd11 txfrmbd10 txfrmbd9 txfrmbd8 33bh 7:0 txfrmbd7 txfrmbd6 txfrmbd5 txfrmbd4 txfrmbd3 txfrmbd2 txfrmbd1 txfrmbd0 note that the addresses in the table above are the indirect addresses that must be provided to the su.macawh and su.macawl. all unused and reserved locations must be initialized to zero for proper operation.
DS33Z11 ethernet mapper 73 of 169 9.2 global register definitions functions contained in the global registers include: fram er reset, liu reset, device id, bert interrupt status, framer interrupt status, mclk configuration, and bpclk c onfiguration. these registers are preserved to provide code compatibility with the multiport devices in this product family. the global registers bit descriptions are presented below. register name: gl.idrl register description: global id low register register address: 00h bit # 7 6 5 4 3 2 1 0 name id07 id06 id05 id04 id03 id02 id01 id00 default 0 0 1 1 0 0 0 0 bit 7: id07 reserved for future use bit 6: id06 reserved for future use bit 5: id05 if this bit is set the device contains a rmii interface bit 4: id04 if this bit is set the device contains a mii interface bit 3: id03 if this bit is set the device contains an ethernet phy bits 0-2: id00-id02 a three-bit count that is equal to 000b for the first die revision, and is incremented with each successive die revision. may not match the two-letter die revision code on the top brand of the device. register name: gl.idrh register description: global id high register register address: 01h bit # 7 6 5 4 3 2 1 0 name id15 id14 id13 id12 id11 id10 id09 id08 default 0 0 0 0 0 0 1 0 bits 5-7: id13-15 number of ports in the device ? 1. (i.e. 000 = 1 port) bit 4: id12 if this bit is set the device has liu functionality bit 3: id11 if this bit is set the device has a framer bit 2: id10 reserved for future use bit 1: id09 if this bit is set the device has hdlc or x.86 encapsulation bit 0: id08 if this bit is set the device has inverse multiplexing functionality
DS33Z11 ethernet mapper 74 of 169 register name: gl.cr1 register description: global control register 1 register address: 02h bit # 7 6 5 4 3 2 1 0 name - - - - - ref_clko intm rst default 0 0 0 bit 2: ref_clko off (ref_clko) this bit determines if the ref_clko is turned off 1 = ref_clko is disabled and outputs an active low signal. 0 = ref_clko is active and in accordance with rmii/mii selection bit 1: int pin mode (intm) this bit determines the inactive mode of the int pin. the int pin always drives low when active. 1 = pin is high impedance when not active 0 = pin drives high when not active bit 0: reset (rst). when this bit is set to 1, all of the internal data path and status and control registers (except this rst bit), on all ports, are reset to their default st ate. this bit must be set high for a minimum of 100ns. 0 = normal operation 1 = reset and force all internal registers to their default values register name: gl.blr register description: global bert connect register register address: 03h bit # 7 6 5 4 3 2 1 0 name - - - - - - - blc1 default 0 0 0 0 0 0 0 0 bit 0: bert connect 1 (blc1) if this bit is set to 1, the bert is connected to serial interface 1. the bert transmitter is connected to the transmit serial port and receive to receive serial port. when the bert is connected, normal data transfer is interrupted. note that connecting the bert overrides a connection to the serial interface, if a connection exists. when the bert is disconnected, the connection is restored. the bert is unavailable in hardware mode.
DS33Z11 ethernet mapper 75 of 169 register name: gl.rtcal register description: global receive and transmit serial port clock activity latched status register address: 04h bit # 7 6 5 4 3 2 1 0 name - - - rlcals1 - - - tlcals1 default - - - - - - - - bit 4: receive serial interface clock activity latched status 1 (rlcals1) this bit is set to 1 if the receive clock for serial interface 1 has activity. this bit is cleared upon read. bit 0: transmit serial interface clock activity latched status 1 (tscals1) this bit is set to 1 if the transmit clock for serial interface 1 has activity. this bit is cleared upon read. register name: gl.srcals register description: global sdram reference clock activity latched status register address: 05h bit # 7 6 5 4 3 2 1 0 name - - - - - - refclks syscls default - - - - - - - - bit 1: reference clock activity latched status (refclks) this bit is set to 1 if ref_clk has activity. this bit is cleared upon read. bit 0: system clock input latched status (syscls) this bit is set to 1 if sysclki has activity. this bit is cleared upon read. register name: gl.lie register description: global serial interface interrupt enable register address: 06h bit # 7 6 5 4 3 2 1 0 name - - - lin1tie - - - lin1rie default 0 0 0 0 0 0 0 0 bit 4: serial interface 1 tx interrupt enable (line1tie) setting this bit to 1 enables an interrupt on lin1tis bit 0: serial interface 1 rx interrupt enable (line1rie) setting this bit to 1 enables an interrupt on lin1ris
DS33Z11 ethernet mapper 76 of 169 register name: gl.lis register description: global serial interface interrupt status register address: 07h bit # 7 6 5 4 3 2 1 0 name - - - lin1tis - - - lin1ris default 0 0 0 0 0 0 0 0 bit 4: serial interface 1 tx interrupt status (line1tis) this bit is set if serial interface 1 transmit has an enabled interrupt generating event. serial interface interrupts consist of hdlc interrupts and x.86 interrupts. bit 0: serial interface 1 rx interrupt status (liner1is) this bit is set if serial interface 1 receive has an enabled interrupt generating event. serial interface interrupts consist of hdlc interrupts and x.86 interrupts. register name: gl.sie register description: global ethernet interface interrupt enable register address: 08h bit # 7 6 5 4 3 2 1 0 name - - - - - - - sub1ie default 0 0 0 0 0 0 0 0 bit 0: ethernet interface 1 interrupt enable (sub1ie) setting this bit to 1 enables an interrupt on sub1s. register name: gl.sis register description: global ethernet interface interrupt status register address: 09h bit # 7 6 5 4 3 2 1 0 name - - - - - - - sub1is default 0 0 0 0 0 0 0 0 bit 0: ethernet interface 1 interrupt status (sub1is) this bit is set to 1 if ethernet interface 1 has an enabled interrupt generating event. the ethernet interface consists of the mac and the rmii/mii port.
DS33Z11 ethernet mapper 77 of 169 register name: gl.trqie register description: global transmit receive queue interrupt enable register address: 0ah bit # 7 6 5 4 3 2 1 0 name - - - tq1ie - - - rq1ie default 0 0 0 0 0 0 0 0 bit 4: transmit queue 1 interrupt enable (tq1ie) setting this bit to 1 enables an interrupt on tq1is. bit 0: receive queue 1 interrupt enable (rq1ie) setting this bit to 1 enables an interrupt on rq1is. register name: gl.trqis register description: global transmit receive queue interrupt status register address: 0bh bit # 7 6 5 4 3 2 1 0 name - - - tq1is - - - rq1is default 0 0 0 0 0 0 0 0 bit 4: transmit queue 1 interrupt enable (tq1is) if this bit is set to 1, the transmit queue 1 has interrupt status event. transmit queue events are transmit queue-crossing thresholds and queue overflows. bit 0: receive queue 1 interrupt status (rq1is) if this bit is set to 1, the receive queue 1 has interrupt status event. receive queue events are transmit queue-crossing thresholds and queue overflows. register name: gl.bie register description: global bert interrupt enable register address: 0ch bit # 7 6 5 4 3 2 1 0 name - - - - - - - bie default 0 0 0 0 0 0 0 0 bit 0: bert interr upt enable (bie) setting this bit to 1 enables an interrupt on bis.
DS33Z11 ethernet mapper 78 of 169 register name: gl.bis register description: global bert interrupt status register address: 0dh bit # 7 6 5 4 3 2 1 0 name - - - - - - - bis default 0 0 0 0 0 0 0 0 bit 0: bert interr upt status (bis) this bit is set to 1 if the bert has an enabled interrupt generating event. register name: gl.con1 register description: connection register for ethernet interface 1 register address: 0eh bit # 7 6 5 4 3 2 1 0 name - - - - - - - line1[0] default 0 0 0 0 0 0 0 1 bit 0: line1[0] this bit is preserved to provide software com patibility with multiport devices. the line1[0] bit selects the ethernet port that is to be connected to the serial interface. note that bi-directional connection is assumed between the serial and ethernet interfaces. the connection register and corresponding queue size must be defined for proper operation. writing a 0 to this r egister will disconnect the connection. when a connection is disconnected, ?1?s are sourced to the serial interface transmit and to the hdlc receiver and the clocks to the hdlc transmitter/receiver are disabled.
DS33Z11 ethernet mapper 79 of 169 register name: gl.c1qpr register description: connection 1 queue pointer reset register address: 12h bit # 7 6 5 4 3 2 1 0 name - - - - c1mrprr c1hwprr c1mhpr c1hrpr default 0 0 0 0 0 0 0 0 bit 3: mac read pointer reset (c1mrprr) if this bit is set to 1, the receive queue read pointer is reset for connection 1. the queue pointer must be reset after a disconnect and before a connection. bit 2: hdlc write pointer reset (c1hwprr) if this bit is set to 1, the receive queue write pointer is reset for connection 1. the queue pointer must be reset after a disconnect and before a connection. bit 1: hdlc read pointer reset (c1mhpr) if this bit is set to 1, the receive queue read pointer is reset for connection 1. the queue pointer must be reset after a disconnect and before a connection. bit 0: mac transmit write pointer reset (c1hrpr) if this bit is set to 1, the receive queue write pointer is reset for connection 1. the queue pointer must be reset after a disconnect and before a connection. register name: gl.bisten register description: bist enable register address: 20h bit # 7 6 5 4 3 2 1 0 name - - - - - - - biste default 0 0 0 0 0 0 0 0 bit 0: bist enable (biste) if this bit is set the DS33Z11 performs bist test on the sdram. normal data communication is halted while bist enable is high. the user must reset the DS33Z11 after completion of bist test before normal dataflow can begin. register name: gl.bistpf register description: bist passfail register address: 21h bit # 7 6 5 4 3 2 1 0 name - - - - - - bistdn bistpf default 0 0 0 0 0 0 0 0 bit 1: bist done (bistdn) if this bit is set to 1, the DS33Z11 has completed the bist test initiated by biste. the pass fail result is available in bistpf. bit 0: bist passfail (bistpf) this bit is equal to 0 after the DS33Z11 performs bist testing on the sdram and the test passes. this bit is set to 1 if the test failed. this bit is valid only after the bist test is complete and the bist dn bit is set. if set this bit can only be cleared by resetting the DS33Z11.
DS33Z11 ethernet mapper 80 of 169 9.3 arbiter registers the arbiter manages the transport between the ethernet port and the serial interface. it is responsible for queuing and dequeuing data to an external sdram. the arbiter handles requests from the hdlc and mac to transfer data to/from the sdram. the base address of the arbiter register space is 0040h. 9.3.1 arbiter register bit descriptions register name: ar.rqsc1 register description: arbiter receive queue size connection register address: 40h bit # 7 6 5 4 3 2 1 0 name rqsc7 rqsc6 rqsc5 rqsc4 rqsc3 rqsc2 rqsc1 rqsc0 default 0 0 1 1 1 1 0 1 bits 0-7: receive queue size (rqsc[0:7]) these 7 bits of the size of receive queue associated with the connection. receive queue is for data arriving from the mac to be sent to the wan. the queue address size is defined in increments of 32 x 2048 bytes. the queue size is ar.rqsc1 multiplied by 32 to determine the number of 2048 byte packets that can be stored in the queue. this queue is constructed in the external sdram . note: queue size of 0 is not allowed and should never be set. register name: ar.tqsc1 register description: arbiter transmit queue size connection 1 register address: 41h bit # 7 6 5 4 3 2 1 0 name tqsc7 tqsc6 tqsc5 tqsc4 tqsc3 tqsc2 tqsc1 tqsc0 default 0 0 0 0 0 0 1 1 bits 0-7: transmit queue size (tqsc[0:7]) this is size of transmit queue associated with the connection. the queue address size is defined in increments of 32 packets. the range of bytes will depend on the external sdram connected to the DS33Z11. transmit queue is the data queue for data arriving on the wan that is sent to the mac. note that queue size of 0 is not allowed and should never be set.
DS33Z11 ethernet mapper 81 of 169 9.4 bert registers register name: bcr register description: bert control register register address: 80h bit # 7 6 5 4 3 2 1 0 name - pmu rnpl rpic mpr aprd tnpl tpic default 0 0 0 0 0 0 0 0 bit 7: this bit must be kept low for proper operation. bit 6: performance monitoring update (pmu) this bit causes a performance monitoring update to be initiated. a 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1). for a second performance monitoring update to be initiated, this bit must be set to 0, and back to 1. if pmu goes low before the pms bit goes high, an update might not be performed. bit 5: receive new pattern load (rnpl) a zero to one transition of this bit will cause the programmed test pattern (qrss, pts, plf [4:0}, ptf [4:0], and bsp [31:0]) to be loaded in to the receive pattern generator. this bit must be changed to zero and back to one for another pattern to be loaded. loading a new pattern will forces the receive pattern generator out of the ?sync? state which causes a resynchronization to be initiated. note: qrss, pts, plf [4:0}, ptf [4:0], and bsp [31:0] must not change from the time this bit transitions from 0 to 1 until four rclki clock cycles after this bit transitions from 0 to 1. bit 4: receive pattern inversion control (rpic) when 0, the receive incoming data stream is not altered. when 1, the receive incoming data stream is inverted. bit 3: manual pattern resynchronization (mpr) a zero to one transition of this bit will cause the receive pattern generator to resynchronize to the incoming pattern. this bit must be changed to zero and back to one for another resynchronization to be initiated. note: a manual resynchronization forces the receive pattern generator out of the ?sync? state. bit 2: automatic pattern resynchronization disable (aprd) when 0, the receive pattern generator will automatically resynchronize to the incoming pattern if six or more times during the current 64-bit window the incoming data stream bit and the receive pattern generator output bit did not match. when 1, the receive pattern generator will not automatically resynchronize to the incoming pattern. note: automatic synchronization is prevented by not allowing the receive pattern generator to automatically exit the ?sync? state. bit 1: transmit new pattern load (tnpl) a zero to one transition of this bit will cause the programmed test pattern (qrss, pts, plf[4:0}, ptf[4:0], and bsp[31:0]) to be loaded in to the transmit pattern generator. this bit must be changed to zero and back to one for another pattern to be loaded. note: qrss, pts, plf[4:0}, ptf[4:0], and bsp[31:0] must not change from the time this bit transitions from 0 to 1 until four tclki clock cycles after this bit transitions from 0 to 1. bit 0: transmit pattern inversion control (tpic) when 0, the transmit outgoing data stream is not altered. when 1, the transmit outgoing data stream is inverted.
DS33Z11 ethernet mapper 82 of 169 register name: bpclr register description: bert pattern configuration low register register address: 82h bit # 7 6 5 4 3 2 1 0 name - qrss pts plf4 plf3 plf2 plf1 plf0 default 0 0 0 0 0 0 0 0 bit 6: qrss enable (qrss) when 0, the pattern generator configuration is controlled by pts, plf[0:4], and ptf[0:4], and bsp[0:31]. when 1, the pattern generator configuration is forced to a qrss pattern with a generating polynomial of x 20 + x 17 + 1. the output of the pattern generator is forced to one if the next fourteen output bits are all zero. bit 5: pattern type select (pts) when 0, the pattern is a prbs pattern. when 1, the pattern is a repetitive pattern. register name: bpchr register description: bert pattern configuration high register register address: 83h bit # 7 6 5 4 3 2 1 0 name - - - ptf4 ptf3 ptf2 ptf1 ptf0 default 0 0 0 0 0 0 0 0 bits 4 to 0: pattern tap feedback (ptf[4:0]) these five bits control the prbs ?tap? feedback of the pattern generator. the ?tap? feedback is from bit y of the pattern generator (y = ptf[4:0] +1). these bits are ignored when programmed for a repetitive pattern. for a prbs signal, the feedback is an xor of bit n and bit y. the values possible are outlined in section 8.15 .
DS33Z11 ethernet mapper 83 of 169 register name: bspb0r register description: bert pattern byte0 register register address: 84h bit # 7 6 5 4 3 2 1 0 name bsp7 bsp6 bsp5 bsp4 bsp3 bsp2 bsp1 bsp0 default 0 0 0 0 0 0 0 0 bits 0 to 7: bert pattern (bsp[7:0]) lower eight bits of 32 bits. register description follows next register. register name: bspb1r register description: bert pattern byte 1 register register address: 85h bit # 7 6 5 4 3 2 1 0 name bsp15 bsp14 bsp13 bsp12 bsp11 bsp10 bsp9 bsp8 default 0 0 0 0 0 0 0 0 bits 0 to 7: bert pattern (bsp[15:8]) 8 bits of 32 bits. register description below. register name: bspb2r register description: bert pattern byte2 register register address: 86h bit # 7 6 5 4 3 2 1 0 name bsp23 bsp22 bsp21 bsp20 bsp19 bsp18 bsp17 bsp16 default 0 0 0 0 0 0 0 0 bits 0 to 7: bert pattern (bsp[23:16]) 8 bits of 32 bits. register description below. register name: bspb3r register description: bert seed/pattern byte3 register register address: 87h bit # 7 6 5 4 3 2 1 0 name bsp31 bsp30 bsp29 bsp28 bsp27 bsp26 bsp25 bsp24 default 0 0 0 0 0 0 0 0 bits 0 to 8: bert pattern (bsp[31:24]) upper 8 bits of 32 bits. register description below. bert pattern (bsp[31:0]) these 32 bits are the programmable seed for a transmit prbs pattern, or the programmable pattern for a transmit or receive repetitive pattern. bsp(31) is the first bit output on the transmit side for a 32-bit repetitive pattern or 32-bit length prbs. bsp(31) is the first bit input on the receive side for a 32- bit repetitive pattern.
DS33Z11 ethernet mapper 84 of 169 register name: teicr register description: transmit error insertion control register register address: 88h bit # 7 6 5 4 3 2 1 0 name - - tier2 tier1 tier0 bei tsei - default 0 0 0 0 0 0 0 0 bits 3 ? 5: transmit error insertion rate (teir[2:0]) these three bits indicate the rate at which errors are inserted in the output data stream. one out of every 10 n bits is inverted. teir[2:0] is the value n. a teir[2:0] value of 0 disables error insertion at a specific rate. a teir[2:0] value of 1 result in every 10 th bit being inverted. a teir[2:0] value of 2 results in every 100 th bit being inverted. error insertion starts when this register is written to with a teir[2:0] value that is non-zero. if this register is written to during the middle of an error insertion process, the new error rate is started after the next error is inserted. bit 2: bit error insertion enable (bei) when 0, single bit error insertion is disabled. when 1, single bit error insertion is enabled. bit 1: transmit single error insert (tsei) this bit causes a bit error to be inserted in the transmit data stream if and single bit error insertion is enabled. a 0 to 1 transition causes a single bit error to be inserted. for a second bit error to be inserted, this bit must be set to 0, and back to 1. note: if this bit transitions more than once between error insertion opportunities, only one error is inserted. all other bits in this register besides bei and tsei and tier must be reset to 0 for proper operation. register name: bsr register description: bert status register register address: 8ch bit # 7 6 5 4 3 2 1 0 name - - - - pms - bec oos default 0 0 0 0 0 0 0 0 bit 3: performance monitoring update status (pms) this bit indicates the status of the receive performance monitoring register (counters) update. this bit will transition from low to high when the update is completed. pms is asynchronously forced low when the pmu bit goes low. tclki and rclki must be present. bit 1: bit error count (bec) when 0, the bit error count is zero. when 1, the bit error count is one or more. bit 0: out of synchronization (oos) when 0, the receive pattern generator is synchronized to the incoming pattern. when 1, the receive pattern generator is not synchronized to the incoming pattern.
DS33Z11 ethernet mapper 85 of 169 register name: bsrl register description: bert status register latched register address: 8eh bit # 7 6 5 4 3 2 1 0 name - - - - pmsl bel becl oosl default - - - - - - - - bit 3: performance monitor update status latched (pmsl) this bit is set when the pms bit transitions from 0 to 1. bit 2: bit error detected latched (bel) this bit is set when a bit error is detected. bit 1: bit error count latched (becl) this bit is set when the bec bit transitions from 0 to 1. bit 0: out of synchronization latched (oosl) this bit is set when the oos bit changes state. register name: bsrie register description: bert status register interrupt enable register address: 90h bit # 7 6 5 4 3 2 1 0 name - - - - pmsie beie becie oosie default 0 0 0 0 0 0 0 0 bit 3: performance monitoring update status interrupt enable (pmsie) this bit enables an interrupt if the pmsl bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: bit error interrupt enable (beie) this bit enables an interrupt if the bel bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: bit error count interrupt enable (becie) this bit enables an interrupt if the becl bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: out of synchronization interrupt enable (oosie) this bit enables an interrupt if the oosl bit is set. 0 = interrupt disabled 1 = interrupt enabled
DS33Z11 ethernet mapper 86 of 169 register name: rbecb0r register description: receive bit error count byte 0 register register address: 94h bit # 7 6 5 4 3 2 1 0 name bec7 bec6 bec5 bec4 bec3 bec2 bec1 bec0 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit error count (bec[0:7]) lower eight bits of 24 bits. register description below. register name: rbecb1r register description: receive bit error count byte 1 register register address: 95h bit # 7 6 5 4 3 2 1 0 name bec15 bec14 bec13 bec12 bec11 bec10 bec9 bec8 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit error count (bec[8:15]) eight bits of a 24 bit value. register description below. register name: rbecr2 register description: receive bit error count byte 2 register register address: 96h bit # 7 6 5 4 3 2 1 0 name bec23 bec22 bec21 bec20 bec19 bec18 bec17 bec16 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit error count (bec[16:23]) upper 8-bits of the register. bit error count (bec[0:23]) these twenty-four bits indicate the number of bit errors detected in the incoming data stream. this count stops incrementing when it reac hes a count of ff ffffh. the associated bit error counter will not incremented when an oos condition exists. register name: rbcb0 register description: receive bit count byte 0 register register address: 98h bit # 7 6 5 4 3 2 1 0 name bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit count (bc[0:7]) eight bits of a 32 bit value. register description below. register name: rbcb1 register description: receive bit count byte 1 register #1 register address: 99h
DS33Z11 ethernet mapper 87 of 169 bit # 7 6 5 4 3 2 1 0 name bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit count (bc[8:15]) eight bits of a 32 bit value. register description below. register name: rbcb2 register description: receive bit count byte 2 register register address: 9ah bit # 7 6 5 4 3 2 1 0 name bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit count (bc[16:23]) eight bits of a 32 bit value. register description below. register name: rbcb3 register description: receive bit count byte 3 register register address: 9bh bit # 7 6 5 4 3 2 1 0 name bc31 bc30 bc29 bc28 bc27 bc26 bc25 bc24 default 0 0 0 0 0 0 0 0 bits 0 - 7: bit count (bc[24:31]) upper 8-bits of the register. bit count (bc[0:31]) these thirty-two bits indicate the number of bits in the incoming data stream. this count stops incrementing when it reaches a count of ffff ffffh. the associated bi t counter will not incremented when an oos condition exists.
DS33Z11 ethernet mapper 88 of 169 9.5 serial interface registers the serial interface contains the serial hdlc transpor t circuitry and the associated serial port. the serial interface register map consists of registers that ar e common functions, transmit functions, and receive functions. bits that are underlined are read-only; all other bits can be written. all reserved registers and bits with ?-? designation should be written to zero, unless specifica lly noted in the register definition. when read, the information from reserved registers and bi ts designated with ?-? should be discarded. counter registers are updated by asserting (low to high transition) the associated performance monitoring update signal (xxpmu). during the counter register update process, the associated performance monitoring status signal (xxpms) is deasserted. the counter register update process consists of loading the counter register with the current count, resetting the counter, forcing the zero count status indication low for one clock cycle, and then asserting xxpms. no events are missed during this update procedure. a latched bit is set when the associated event occurs, and remains set until it is cleared by reading. once cleared, a latched bit will not be set again until the associated event occurs again. reserved configuration bits and registers should be written to zero. 9.5.1 serial interface transmit and common registers serial interface transmit registers are used to control the hdlc transmitter associated with each serial interface. the register map is shown in the following table. note that throughout this document the hdlc processor is also referred to as a ?packet processor.? 9.5.2 serial interface transmit register bit descriptions register name: li.tslcr register description: transmit serial interface configuration register register address: 0c0h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tdenplt default 0 0 0 0 0 0 0 0 bit 0: transmit data enable polarity (tdenplt) if set to 1, tden is active low for enable. in the default mode, when tden is logic high, the data is enabled and output by the DS33Z11. register name: li.rstpd register description: serial interface reset register register address: 0c1h bit # 7 6 5 4 3 2 1 0 name - - - - - - reset - default 0 0 0 0 0 0 0 0 bit 1: reset if this bit set to 1, the data path and control and status for this interface are reset. the serial interface is held in reset as long as this bit is high. this bit must be high for a minimum of 200 nsec for a valid reset to occur.
DS33Z11 ethernet mapper 89 of 169 register name: li.lpbk register description: serial interface loopback control register register address: 0c2h bit # 7 6 5 4 3 2 1 0 name - - - - - - - qlp default 0 0 0 0 0 0 0 0 bit 0: queue loopback enable (qlp) if this bit set to 1, data received on the serial interface is looped back to the serial interface transmitter. received data will not be sent from the serial interface to the ethernet interface. buffered packet data will remain in queue until the loopback is removed. 9.5.3 transmit hdlc processor registers register name: li.tppcl register description: transmit packet processor control low register register address: 0c4h bit # 7 6 5 4 3 2 1 0 name - - tfad tf16 tifv tsd tbre tiaei default 0 0 0 0 0 0 0 0 note: the user should take care not to modify this register value during packet error insertion. bits 5 - 6: transmit fcs append disable (tfad) ? this bit controls whether or not an fcs is appended to the end of each packet. when equal to 0, the calculated fcs bytes are appended to packets. when set to 1, packets are transmitted without fcs. in x.86 mode, fcs is always 32 bits and is always appended to the packet. bit 4: transmit fcs-16 enable (tf16) ? when 0, the fcs processing uses a 32-bit fcs. when 1, the fcs processing uses a 16-bit fcs. in x.86 mode, 32-bit fcs processing is enabled. bit 3: transmit bit synchronous inter-frame fill value (tifv) ? when 0, inter-frame fill is done with the flag sequence (7eh). when 1, inter-frame fill is done with all '1's. this bit is ignored in byte synchronous mode. in x.86 mode the interframe flag is always 7e. bit 2: transmit scrambling disable (tsd) ? when equal to 0, x 43 +1 scrambling is performed. when set to 1, scrambling is disabled. note that in hardware mode, tr ansmit scrambling is controlled by the scd hardware pin. bit 1: transmit bit re ordering enable (tbre) ? when equal to 0, bit reordering is disabled (the first bit transmitted is from the msb of the transmit fifo byte tfd [7]). when set to 1, bit reordering is enabled (the first bit transmitted is from the lsb of the transmit fifo byte tfd [0]). note that this function can be controlled in hardware mode with the breo hardware pin. bit 0: transmit initiate automatic error insertion (tiaei) ? this write-only bit initiates error insertion. see the li.tephc register definition for details of usage.
DS33Z11 ethernet mapper 90 of 169 register name: li.tifgc register description: transmit inter-frame gapping control register register address: 0c5h bit # 7 6 5 4 3 2 1 0 name tifg7 tifg6 tifg5 tifg4 tifg3 tifg2 tifg1 tifg0 default 0 0 0 0 0 0 0 1 bits 0 - 7: transmit inter-frame gapping (tifg[7:0]) ? these eight bits indicate the number of additional flags and bytes of inter-frame fill to be inserted between packets. the number of flags and bytes of inter-frame fill between packets is at least the value of tifg[7:0] plus 1. note: if inter-frame fill is set to all 1?s, a tfig value of 2 or 3 will result in a flag, two bytes of 1?s, and an additional flag between packets. register name: li.teplc register description: transmit errored packet low control register register address: 0c6h bit # 7 6 5 4 3 2 1 0 name tpen7 tpen6 tpen5 tpen 4 tpen3 tpen2 tpen1 tpen0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit errored packet insertion number (tpen[7:0]) ? these eight bits indicate the total number of errored packets to be transmitted when triggered by tiaei. error insertion will end after this number of errored packets have been transmitted. a value of ffh results in continuous errored packet insertion at the specified rate.
DS33Z11 ethernet mapper 91 of 169 register name: li.tephc register description: transmit errored packet high control register register address: 0c7h bit # 7 6 5 4 3 2 1 0 name meims tper6 tper5 tper 4 tper3 tper2 tper1 tper0 default 0 0 0 0 0 0 0 0 bit 7: manual error insert mode select (meims) ? when 0, the transmit manual error insertion signal (tmei) will not cause errors to be inserted. when 1, tmei will cause an error to be inserted when it transitions from a 0 to a 1. note: enabling tmei does not disable error insertion using tcer[6:0] and tcen[7:0]. bits 0 ? 6: transmit errored packet insertion rate (tper[6:0]) ? these seven bits indicate the rate at which errored packets are to be output. one out of every x * 10 y packets is to be an errored packet. tper[3:0] is the value x, and tper[6:4] is the value y which has a maximum value of 6. if tper[3:0] has a value of 0h errored packet insertion is disabled. if tper[6:4] has a value of 6xh or 7xh the errored packet rate is x * 10 6 . a tper[6:0] value of 01h results in every packet being errored. a tper[6:0] value of 0fh results in every 15 th packet being errored. a tper[6:0] value of 11h results in every 10 th packet being errored. to initiate automati c error insertion, use the following routine: 1) configure li.teplc and li.tephc for the desired error insertion mode. 2) write the li.tppcl.tiaei bit to 1. note that this bit is write-only. 3) if not using continuous error insertion (li.tpelc is not equal to ffh), the user should monitor the li.tppsr.tepf bit for completion of the error insertion. if interrupt on completion of error insertion is enabled (li.tppsrie.tepfie = 1), the user only needs to wait for the interrupt condition. 4) proceed with the cleanup routine listed below. cleanup routine: 1) write li.teplc and li.tephc each to 00h. 2) write the li.tppcl.tiaei bit to 0.
DS33Z11 ethernet mapper 92 of 169 register name: li.tppsr register description: transmit packet processor status register register address: 0c8h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tepf default 0 0 0 0 0 0 0 0 bit 0: transmit errored packet insertion finished (tepf) ? this bit is set when the number of errored packets indicated by the tpen[7:0] bits in the tepc register have been transmitted. this bit is cleared when errored packet insertion is disabled, or a new errored packet insertion process is initiated. register name: li.tppsrl register description: transmit packet processor status register latched register address: 0c9h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tepfl default - - - - - - - - bit 0: transmit errored packet insertion finished latched (tepfl) ? this bit is set when the tepf bit in the tppsr register transitions from zero to one. register name: li.tppsrie register description: transmit packet processor status register interrupt enable register address: 0cah bit # 7 6 5 4 3 2 1 0 name - - - - - - - tepfie default 0 0 0 0 0 0 0 0 bit 0: transmit errored packet insertion finished interrupt enable (tepfie) ? this bit enables an interrupt if the tepfl bit in the li.tppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled
DS33Z11 ethernet mapper 93 of 169 register name: li.tpcr0 register description: transmit packet count byte 0 register address: 0cch bit # 7 6 5 4 3 2 1 0 name tpc7 tpc6 tpc5 tpc4 tpc3 tpc2 tpc1 tpc0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit packet count (tpc[7:0]) ? eight bits of 24 bit value. register description below. register name: li.tpcr1 register description: transmit packet count byte 1 register address: 0cdh bit # 7 6 5 4 3 2 1 0 name tpc15 tpc14 tpc13 tpc12 tpc11 tpc10 tpc9 tpc8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit p acket count (tpc[15:8]) ? eight bits of 24 bit value. register description below. register name: li.tpcr2 register description: transmit packet count byte 2 register address: 0ceh bit # 7 6 5 4 3 2 1 0 name tpc23 tpc22 tpc21 tpc20 tpc19 tpc18 tpc17 tpc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit packet count (tpc[23:16]) ? these twenty-four bits indicate the number of packets extracted from the transmit fifo and output in the outgoing data stream.
DS33Z11 ethernet mapper 94 of 169 register name: li.tbcr0 register description: transmit byte count byte 0 register address: 0d0h bit # 7 6 5 4 3 2 1 0 name tbc7 tbc6 tbc5 tbc4 tbc3 tbc2 tbc1 tbc0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit byte count (tbc[0:7]) ? eight bits of 32 bit value. register description below. register name: li.tbcr1 register description: transmit byte count byte 1 register address: 0d1h bit # 7 6 5 4 3 2 1 0 name tbc15 tbc14 tbc13 tbc12 tbc11 tbc10 tbc9 tbc8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit byte count (tbc[15:8]) - eight bits of 32 bit value. register description below. register name: li.tbcr2 register description: transmit byte count byte 2 register address: 0d2h bit # 7 6 5 4 3 2 1 0 name tbc23 tbc22 tbc21 tbc20 tbc19 tbc18 tbc17 tbc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit byte count (tbc[23:16]) - eight bits of 32 bit value. register description below. register name: li.tbcr3 register description: transmit byte count byte 3 register address: 0d3h bit # 7 6 5 4 3 2 1 0 name tbc31 tbc30 tbc29 tbc28 tbc27 tbc26 tbc25 tbc24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit byte count (tbc[31:24]) ? these thirty-two bits indicate the number of packet bytes inserted in the outgoing data stream.
DS33Z11 ethernet mapper 95 of 169 register name: li.tmei register description: transmit manual error insertion register address: 0d4h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tmei default 0 0 0 0 0 0 0 0 bit 0: transmit manual error insertion (tmei) a zero to one transition will insert a single error in the transmit direction. register name: li.thpmuu register description: serial interface transmit hdlc pmu update register register address: 0d6h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tpmuu default 0 0 0 0 0 0 0 0 bit 0: transmit pmu update (tpmuu) this signal causes the transmit cell/packet processor block performance monitoring registers (counters) to be updated. a 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1). this update updates performance monitoring counters for the serial interface. register name: li.thpmus register description: serial interface transmit hdlc pmu update status register register address: 0d7h bit # 7 6 5 4 3 2 1 0 name - - - - - - - tpmus default 0 0 0 0 0 0 0 0 bit 0: transmit pmu update status (tpmus) this bit is set when the transmit pmu update is completed. this bit is cleared when tpmuu is reset.
DS33Z11 ethernet mapper 96 of 169 9.5.4 x.86 registers x.86 transmit and common registers are used to control the operation of the x.86 encoder and decoder. register name: li.tx86ede register description: x.86 encoding decoding enable register address: 0d8h bit # 7 6 5 4 3 2 1 0 name - - - - - - - x86ed default 0 0 0 0 0 0 0 0 bit 0: x.86 encoding decoding (x86ed) if this bit is set to 1, x.86 encoding and decoding is enabled for the transmit and receive paths. the mac frame is encapsulated in the x.86 frame for transmit and the x.86 headers are checked for in the received data. if x.86 functionality is selected, the x.86 receiver byte boundary is provided by the rbsync signal and the DS33Z11 provides the transmit byte synchronization tbsync. no hdlc encapsulation is performed. register name: li.trx86a register description: transmit receive x.86 address register address: 0d9h bit # 7 6 5 4 3 2 1 0 name x86tra7 x86tra6 x86tra5 x86tra 4 x86tra3 x86tra2 x86tra1 x86tra0 default 0 0 0 0 0 1 0 0 bits 0 - 7: x86 transmit receive address (x86tra0-7) this is the address field for the x.86 transmitter and for the receiver. the register default value is 0x04. register name: li.trx8c register description: transmit receive x.86 control register address: 0dah bit # 7 6 5 4 3 2 1 0 name x86trc7 x86trc6 x86trc5 x86trc4 x86trc3 x86trc2 x86trc1 x86trc0 default 0 0 0 0 0 0 1 1 bits 0 - 7: x86 transmit receive control (x86trc0-7) this is the control field for the x.86 transmitter and expected value for the receiver. the register is reset to 0x03 register name: li.trx86sapih register description: transmit receive x.86 sapih register address: 0dbh bit # 7 6 5 4 3 2 1 0 name trsapih7 trsapih6 trsapih5 trsapih4 trsapih3 trsapi h2 trsapih1 trsapih0 default 1 1 1 1 1 1 1 0 bits 0 - 7: x86 transmit receive address (trsapih0-7) this is the address field for the x.86 transmitter and expected for the receiver. the register is reset to 0xfe.
DS33Z11 ethernet mapper 97 of 169 register name: li.trx86sapil register description: transmit receive x.86 sapil register address: 0dch bit # 7 6 5 4 3 2 1 0 name trsapil7 trsapil6 trsapi l5 trsapil4 trsapil3 tr sapil2 trsapil1 trsapil0 default 0 0 0 0 0 0 0 1 bits 0 ? 7: x86 transmit receive control (trsapil0-7) this is the address field for the x.86 transmitter and expected value for the receiver. the register is reset to 0x01 register name: li.cir register description: committed information rate register address: 0ddh bit # 7 6 5 4 3 2 1 0 name cire cir6 cir5 cir4 cir3 cir2 cir1 cir0 default 0 0 0 0 0 0 0 1 bit 7: committed information rate enable (cire) set this bit to 1 to enable the committed information rate controller feature. bits 0 ? 6: committed information rate (cir0-6) these bits provide the value for the committed information rate. the value is multiplied by 500 kbps to get the cir value. the user must ensure that the cir value is less than or equal to the maximum serial interface transmit rate. the valid range is from 1 to 104. any values outside this range will result in unpredictable behavior. note that a value of 104 translates to a 52 mbps line rate. hence if the cir is above the line rate, the rate is not restricted by the cir. for instance, if using a t1 line and the cir is programmed with a value of 104, it has no effect in restricting the rate.
DS33Z11 ethernet mapper 98 of 169 9.5.5 receive serial interface serial receive registers are used to control the hdlc receiver associated with each serial interface. note that throughout this document hdlc processor is also referred to as ?packet processor?. the receive packet processor block has seventeen registers. 9.5.5.1 register bit descriptions register name: li.rslcr register description: receive serial interface configuration register register address: 100h bit # 7 6 5 4 3 2 1 0 name - - - - - - - rdenplt default 0 0 0 0 0 0 0 0 bit 0: receive data enable polarity (rdenplt) receive data enable polarity. if set to 1, rden low enables reception of the bit. register name: li.rppcl register description: receive packet processor control low register register address: 101h bit # 7 6 5 4 3 2 1 0 name - - rfpd rf16 rfed rdd rbre rcce default 0 0 0 0 0 0 0 0 bit 5: receive fcs processing disable (rfpd) ? when equal to 0, fcs processing is performed and fcs is appended to packets. when set to 1, fcs processing is disabled (the packets do not have an fcs appended). in x.86 mode, fcs processing is always enabled. bit 4: receive fcs-16 enable (rf16) ? when 0, the error checking circuit uses a 32-bit fcs. when 1, the error checking circuit uses a 16-bit fcs. this bit is ignored when fcs processing is disabled. in x.86 mode, the fcs is always 32 bits. bit 3: receive fcs extraction disable (rfed) ? when 0, the fcs bytes are discarded. when 1, the fcs bytes are passed on. this bit is ignored when fcs processing is disabled. in x.86 mode, fcs bytes are discarded. bit 2: receive descrambling disable (rdd) ? when equal to 0, x 43 +1 descrambling is performed. when set to 1, descrambling is disabled. bit 1: receive bit re ordering enable (rbre) ? when equal to 0, reordering is disabled and the first bit received is expected to be the msb dt [7] of the byte. when set to 1, bit reordering is enabled and the first bit received is expected to be the lsb dt [0] of the byte. note that function is controlled by the breo in hardware mode. bit 0: receive clear channel enable (rcce) ? when equal to 0, packet processing is enabled. when set to 1, the device is in clear channel mode and all packet-processing functions except descrambling and bit reordering are disabled.
DS33Z11 ethernet mapper 99 of 169 register name: li.rmpscl register description: receive maximum packet size control low register register address: 102h bit # 7 6 5 4 3 2 1 0 name rmx7 rmx6 rmx5 rmx4 rmx3 rmx2 rmx1 rmx0 default 1 1 1 0 0 0 0 0 bits 0 - 7: receive maximum packet size (rmx[7:0]) eight bits of a sixteen bit value. register description below. register name: li.rmpsch register description: receive maximum packet size control high register register address: 103h bit # 7 6 5 4 3 2 1 0 name rmx15 rmx14 rmx13 rmx12 rmx11 rmx10 rmx9 rmx8 default 0 0 0 0 0 1 1 1 bits 0-7: receive maximum packet size (rmx[8:15]) these sixteen bits indicate the maximum allowable packet size in bytes. the size includes the fcs bytes, but excludes bit/byte stuffing. note: if the maximum packet size is less than the minimum packet size, all packets are discarded. when packet processing is disabled, these sixteen bits indicate the "packet" size the incoming data is to be broken into. the maximum packet size allowable is 2016 bytes plus the fcs bytes. any values programmed that are greater than 2016 + fcs will have the same effect as 2016+ fcs value. in x.86 mode, the x.86 encapsulation bytes are included in maximum size control. register name: li.rppsr register description: receive packet processor status register register address: 104h bit # 7 6 5 4 3 2 1 0 name - - - - - repc rapc rspc default 0 0 0 0 0 0 0 0 bit 2: receive fcs errored packet count (repc) this read only bit indicates that the receive fcs errored packet count is non-zero. bit 1: receive aborted packet count (rapc) this read only bit indicates that the receive aborted packet count is non-zero. bit 0: receive size violation packet count (rspc) this read only bit indicates t hat the receive size violation packet count is non-zero.
DS33Z11 ethernet mapper 100 of 169 register name: li.rppsrl register description: receive packet processor status register latched register address: 105h bit # 7 6 5 4 3 2 1 0 name repl rapl ripdl rspdl rlpdl repcl rapcl rspcl default - - - - - - - - bit 7: receive fcs errored packet latched (repl) this bit is set when a packet with an errored fcs is detected. bit 6: receive aborted packet latched (rapl) this bit is set when a packet with an abort indication is detected. bit 5: receive invalid packet detected latched (ripdl) this bit is set when a packet with a non-integer number of bytes is detected. bit 4: receive small packet detected latched (rspdl) this bit is set when a packet smaller than the minimum packet size is detected. bit 3: receive large packet detected latched (rlpdl) this bit is set when a packet larger than the maximum packet size is detected. bit 2: receive fcs errored packet count latched (repcl) this bit is set when the repc bit in the rppsr register transitions from zero to one. bit 1: receive aborted p acket count latched (rapcl) this bit is set when the rapc bit in the rppsr register transitions from zero to one. bit 0: receive size violati on packet count latched (rspcl) this bit is set when the rspc bit in the rppsr register transitions from zero to one.
DS33Z11 ethernet mapper 101 of 169 register name: li.rppsrie register description: receive packet processor status register interrupt enable register address: 106h bit # 7 6 5 4 3 2 1 0 name repie rapie ripdie rspdie rlpdie repcie rapcie rspcie default 0 0 0 0 0 0 0 0 bit 7: receive fcs errored packet interrupt enable (repie) this bit enables an interrupt if the repl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 6: receive aborted packet interrupt enable (rapie) this bit enables an interrupt if the rapl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 5: receive invalid packet detected interrupt enable (ripdie) this bit enables an interrupt if the ripdl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 4: receive small packet detected interrupt enable (rspdie) this bit enables an interrupt if the rspdl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 3: receive large packet detected interrupt enable (rlpdie) this bit enables an interrupt if the rlpdl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: receive fcs errored packet count interrupt enable (repcie) this bit enables an interrupt if the repcl bit in the li.rppsrl register is set. must be set low when the packets do not have an fcs appended. 0 = interrupt disabled 1 = interrupt enabled bit 1: receive aborted packet c ount interrupt enable (rapcie) this bit enables an interrupt if the rapcl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: receive size violation packet count interrupt enable (rspcie) this bit enables an interrupt if the rspcl bit in the li.rppsrl register is set. 0 = interrupt disabled 1 = interrupt enabled
DS33Z11 ethernet mapper 102 of 169 register name: li.rpcb0 register description: receive packet count byte 0 register register address: 108h bit # 7 6 5 4 3 2 1 0 name rpc7 rpc6 rpc5 rpc4 rpc3 rpc2 rpc1 rpc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive packet count (rpc [7:0]) eight bits of a 24-bit value. register description below. register name: li.rpcb1 register description: receive packet count byte 1 register register address: 109h bit # 7 6 5 4 3 2 1 0 name rpc15 rpc14 rpc13 rpc12 rpc11 rpc10 rpc09 rpc08 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive packet count (rpc [15:8]) eight bits of a 24-bit value. register description below. register name: li.rpcb2 register description: receive packet count byte 2 register register address: 10ah bit # 7 6 5 4 3 2 1 0 name rpc23 rpc22 rpc21 rpc20 rpc19 rpc18 rpc17 rpc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive p acket count (rpc [23:16]) these twenty-four bits indicate the number of packets stored in the receive fifo without an abort indication. note: pa ckets discarded due to system loopback or an overflow condition are included in this count. this register is valid when clear channel is enabled.
DS33Z11 ethernet mapper 103 of 169 register name: li.rfpcb0 register description: receive fcs errored packet count byte 0 register register address: 10ch bit # 7 6 5 4 3 2 1 0 name rfpc7 rfpc6 rfpc5 rfpc4 rfpc3 rfpc2 rfpc1 rfpc0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive fcs erro red packet count (rfpc[7:0]) eight bits of a 24-bit value. register description below. register name: li.rfpcb1 register description: receive fcs errored packet count byte 1 register register address: 10dh bit # 7 6 5 4 3 2 1 0 name rfpc15 rfpc14 rfpc13 rfpc12 rfpc11 rfpc10 rfpc9 rfpc8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive fcs erro red packet count (rfpc[15:8]) eight bits of a 24-bit value. register description below. register name: li.rfpcb2 register description: receive fcs errored packet count byte 2 register register address: 10eh bit # 7 6 5 4 3 2 1 0 name rfpc23 rfpc22 rfpc21 rfpc20 rfpc19 rfpc18 rfpc17 rfpc16 default 0 0 0 0 0 0 0 0 receive fcs errored p acket count (rfpc[23:16]) these twenty-four bits indicate the number of packets received with an fcs error. the byte count for these packets is included in the receive aborted byte count register rebcr.
DS33Z11 ethernet mapper 104 of 169 register name: li.rapcb0 register description: receive aborted packet count byte 0 register register address: 110h bit # 7 6 5 4 3 2 1 0 name rapc7 rapc6 rapc5 rapc4 rapc3 rapc2 rapc1 rapc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive aborte d packet count (rapc [7:0]) eight bits of a 24-bit value. register description below. register name: li.rapcb1 register description: receive aborted packet count byte 1 register register address: 111h bit # 7 6 5 4 3 2 1 0 name rapc15 rapc14 rapc13 rapc12 rapc11 rapc10 rapc9 rapc8 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive aborted packet count (rapc[15:8]) eight bits of a 24-bit value. register description below. register name: li.rapcb2 register description: receive aborted packet count byte 2 register register address: 112h bit # 7 6 5 4 3 2 1 0 name rapc23 rapc22 rapc21 rapc20 rapc19 rapc18 rapc17 rapc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive aborte d packet count (rapc [23:16]) the twenty-four bit value from these three registers indicates the number of packets received with a packet abort indication. the byte count for these packets is included in the receive aborted byte count register rebcr.
DS33Z11 ethernet mapper 105 of 169 register name: li.rspcb0 register description: receive size violation packet count byte 0 register register address: 114h bit # 7 6 5 4 3 2 1 0 name rspc7 rspc6 rspc5 rspc4 rspc3 rspc2 rspc1 rspc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive size violation packet count (rspc [7:0]) eight bits of a 24-bit value. register description below. register name: li.rspcb1 register description: receive size violation packet count byte 1 register register address: 115h bit # 7 6 5 4 3 2 1 0 name rspc15 rspc14 rspc13 rspc12 rspc11 rspc10 rspc9 rspc8 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive size violation packet count (rspc [15:8]) eight bits of a 24-bit value. register description below. register name: li.rspcb2 register description: receive size violation packet count byte 2 registers register address: 116h bit # 7 6 5 4 3 2 1 0 name rspc23 rspc22 rspc21 rspc20 rspc19 rspc18 rspc17 rspc16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive size viol ation packet count (rspc [23:16]) these twenty-four bits indicate the number of packets received with a packet size violation (below mi nimum, above maximum, or non-integer number of bytes). the byte count for these packets is included in the receive aborted byte count register rebcr.
DS33Z11 ethernet mapper 106 of 169 register name: li.rbc0 register description: receive byte count 0 register register address: 118h bit # 7 6 5 4 3 2 1 0 name rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive byte count (rbc [7:0]) eight bits of a 32-bit value. register description below. register name: li.rbc1 register description: receive byte count 1 register register address: 119h bit # 7 6 5 4 3 2 1 0 name rbc15 rbc14 rbc13 rbc12 rbc11 rbc10 rbc9 rbc8 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive byte count (rbc [15:8]) eight bits of a 32-bit value. register description below. register name: li.rbc2 register description: receive byte count 2 register register address: 11ah bit # 7 6 5 4 3 2 1 0 name rbc23 rbc22 rbc21 rbc20 rbc19 rbc18 rbc17 rbc16 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive byte count (rbc [23:16]) eight bits of a 32-bit value. register description below. register name: li.rbc3 register description: receive byte count 3 register register address: 11bh bit # 7 6 5 4 3 2 1 0 name rbc31 rbc30 rbc29 rbc28 rbc27 rbc26 rbc25 rbc24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive by te count (rbc [31:24]) these thirty-two bits indicate the number of bytes contained in packets stored in the receive fifo without an abort indication. note: bytes discarded due to fcs extraction, system loopback, fifo reset, or an overflow condition may be included in this count.
DS33Z11 ethernet mapper 107 of 169 register name: li.rac0 register description: receive aborted byte count 0 register register address: 11ch bit # 7 6 5 4 3 2 1 0 name rebc7 rebc6 rebc5 rebc4 rebc3 rebc2 rebc1 rebc0 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive abor ted byte count (rbc [7:0]) eight bits of a 32-bit value. register description below. register name: li.rac1 register description: receive aborted byte count 1 register register address: 11dh bit # 7 6 5 4 3 2 1 0 name rebc15 rebc14 rebc13 rebc12 rebc11 rebc10 rebc9 rebc8 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive aborte d byte count (rbc [15:8]) eight bits of a 32-bit value. register description below. register name: li.rac2 register description: receive aborted byte count 2 register register address: 11eh bit # 7 6 5 4 3 2 1 0 name rebc23 rebc22 rebc21 rebc20 rebc19 rebc18 rebc17 rebc16 default 0 0 0 0 0 0 0 0 bits 0 - 7: receive aborte d byte count (rbc [16:23]) eight bits of a 32-bit value. register description below. register name: li.rac3 register description: receive aborted byte count 3 register register address: 11fh bit # 7 6 5 4 3 2 1 0 name rebc31 rebc30 rebc29 rebc28 rebc27 rebc26 rebc25 rebc24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: receive aborted byte count (rebc[31:24]) these thirty-two bits indicate the number of bytes contained in packets stored in the receive fifo with an abort indication. note: bytes discarded due to fcs extraction, system loopback, fifo reset, or an overflow condition may be included in this count.
DS33Z11 ethernet mapper 108 of 169 register name: li.rhpmuu register description: serial interface receive hdlc pmu update register register address: 120h bit # 7 6 5 4 3 2 1 0 name - - - - - - - rpmuu default 0 0 0 0 0 0 0 0 bit 0: receive pmu update (rpmuu) this signal causes the receive cell/packet processor block performance monitoring registers (counters) to be updated. a 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1). this update updates performance-monitoring counters for the serial interface. register name: li.rhpmus register description: serial interface receive hdlc pmu update status register register address: 121h bit # 7 6 5 4 3 2 1 0 name - - - - - - - rpmuus default 0 0 0 0 0 0 0 0 bit 0: receive pmu update status (rpmuus) this bit is set when the transmit pmu update is completed. this bit is cleared when rpmuu is set to 0. register name: li.rx86s register description: receive x.86 latched status register register address: 122h bit # 7 6 5 4 3 2 1 0 name - - - - sapihne sapilne cne ane default - - - - - - - - bit 3: sapi high is not equal to li.trx86sapih latched status (sapihne) this latched status bit is set if sapih is not equal to li.trx86sapih. this latched status bit is cleared upon read. bit 2: sapi low is not equal to li.trx86sapil latched status (sapilne) this latched status bit is set if sapil is not equal to li.trx86sapil. this latched status bit is cleared upon read. bit 1: control is not equal to li.trx8c (cne) this latched status bit is set if the control field is not equal to li.trx8c . this latched status bit is cleared upon read. bit 0: address is not equal to li.trx86a (ane) this latched status bit is set if the x.86 address field is not equal to li.trx86a . this latched status bit is cleared upon read.
DS33Z11 ethernet mapper 109 of 169 register name: li.rx86lsie register description: receive x.86 interrupt enable register address: 123h bit # 7 6 5 4 3 2 1 0 name - - - - sapine01im sapinefeim cne3lim ane4im default 0 0 0 0 0 0 0 0 bit 3: sapi octet not equal to li.trx86sapih interrupt enable (sapine01im) if this bit is set to 1, li.rx86s.sapihne will generate an interrupt. bit 2: sapi octet not equal to li.trx86sap il interrupt enab le (sapinefeim) if this bit is set to 1, li.rx86s.sapilne will generate an interrupt. bit 1: control not equal to li.trx8c interrupt enable (cne3lim) if this bit is set to 1, li.rx86s.cne will generate an interrupt. bit 0: address not equal to li.trx86a interrupt enable (ane4im) if this bit is set to 1, li.rx86s.ane will generate an interrupt. register name: li.tqlt register description: serial interface transmit queue low threshold (watermark) register address: 124h bit # 7 6 5 4 3 2 1 0 name tqlt7 tqlt6 tqlt5 tqlt4 tqlt3 tqlt2 tqlt1 tqlt0 default 0 0 0 0 0 0 0 0 bits 0 - 7: transmit queue low threshold (tqlt[0:7]) the transmit queue low threshold for the connection, in increments of 32 packets of 2048 bytes each. the value of this register is multiplied by 32 * 2048 bytes to determine the byte location of the threshold. note that the transmit queue is for data that was received from the serial interface to be sent to the ethernet interface.
DS33Z11 ethernet mapper 110 of 169 register name: li.tqht register description: serial interface transmit queue high threshold (watermark) register address: 125h bit # 7 6 5 4 3 2 1 0 name tqht7 tqht6 tqht5 tqht4 tqht3 tqht2 tqht1 tqht0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: transmit queue high threshold (tqht[0:7]) the transmit queue high threshold for the connection, in increments of 32 packets of 2048 bytes each. the value of this register is multiplied by 32 * 2048 bytes to determine the byte location of the threshold. note that the transmit queue is for data that was received from the serial interface to be sent to the ethernet interface. register name: li.tqtie register description: serial interface transmit queue cross threshold interrupt enable register address: 126h bit # 7 6 5 4 3 2 1 0 name - - - - tfovfie tqovfie tqhtie tqltie default 0 0 0 0 0 0 0 0 bit 3: transmit fifo overflow for connection interrupt enable (tfovfie) if this bit is set, the watermark interrupt is enabled for tfovfls. bit 2: transmit queue overflow for connection interrupt enable (tqovfie) if this bit is set, the watermark interrupt is enabled for tqovfls. bit 1: transmit queue for connection high threshold interrupt enable (tqhtie) if this bit is set, the watermark interrupt is enabled for tqhts. bit 0: transmit queue for connection low threshold interrupt enable (tqltie) if this bit is set, the watermark interrupt is enabled for tqlts. register name: li.tqctls register description: serial interface transmit queue cross threshold latched status register address: 127h bit # 7 6 5 4 3 2 1 0 name - - - - tfovfls tqovfls tqhtls tqltls default - - - - - - - - bit 3: transmit queue fifo overflowed latched status (tfovfls) this bit is set if the transmit queue fifo has overflowed. this register is cleared after a read. this fifo is for data to be transmitted from the hdlc to be sent to the sdram. bit 2: transmit queue overflow latched status (tqovfls) this bit is set if the transmit queue has overflowed. this register is cleared after a read. bit 1: transmit queue for connection exceeded high threshold latched status (tqhtls) this bit is set if the transmit queue crosses the high watermark. this register is cleared after a read. bit 0: transmit queue for connection exceeded low threshold latched status (tqltls) this bit is set if the transmit queue crosses the low watermark. this register is cleared after a read.
DS33Z11 ethernet mapper 111 of 169 9.6 ethernet interface registers the ethernet interface registers are used to configure rmii/mii bus operation and establish the mac parameters as required by the user. the mac registers cannot be addressed directly from the processor port. the registers below are used to perform indirect read or write operations to t he mac registers. the mac status registers are shown in table 9-7 . accessing the mac registers is described in the section 8.14 . 9.6.1 ethernet interface register bit descriptions register name: su.macradl register description: mac read address low register register address: 140h bit # 7 6 5 4 3 2 1 0 name macra7 macra6 macra5 macra 4 macra3 macra2 macra1 macra0 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read address (macra0-7) low byte of the mac address. used only for read operations. register name: su.macradh register description: mac read address high register register address: 141h bit # 7 6 5 4 3 2 1 0 name macra15 macra14 macra13 macra 12 macra11 macra10 macra9 macra8 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read address (macra8-15) high byte of the mac address. used only for read operations. register name: su.macrd0 register description: mac read data byte 0 register address: 142h bit # 7 6 5 4 3 2 1 0 name macrd7 macrd6 macrd5 macrd4 macrd3 macrd2 macrd1 macrd0 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 0 (macrd0-7) one of four bytes of data read from the mac. valid after a read command has been issued and the su.macrwc.mcs bit is zero.
DS33Z11 ethernet mapper 112 of 169 register name: su.macrd1 register description: mac read data byte 1 register address: 143h bit # 7 6 5 4 3 2 1 0 name macrd15 macrd14 macrd13 macrd1 2 macrd11 macrd10 macrd9 macrd8 0 0 0 0 0 0 0 0 bits 0 - 7: mac read data 1 (macrd8-15) one of four bytes of data read from the mac. valid after a read command has been issued and the su.macrwc.mcs bit is zero. register name: su.macrd2 register description: mac read data byte 2 register address: 144h bit # 7 6 5 4 3 2 1 0 name macrd23 macrd22 macrd21 macrd2 0 macrd19 macrd18 macrd17 macrd16 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 2 (macrd16-23) one of four bytes of data read from the mac. valid after a read command has been issued and the su.macrwc.mcs bit is zero. register name: su.macrd3 register description: mac read data byte 3 register address: 145h bit # 7 6 5 4 3 2 1 0 name macrd31 macrd30 macrd29 macrd2 8 macrd27 macrd26 macrd25 macrd24 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 3 (macrd24-31) one of four bytes of data read from the mac. valid after a read command has been issued and the su.macrwc.mcs bit is zero. register name: su.macwd0 register description: mac write data 0 register address: 146h bit # 7 6 5 4 3 2 1 0 name macwd7 macwd6 macwd5 macw d4 macwd3 macwd2 macwd1 macwd0 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 0 (macwd0-7) one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.macrwc.mcs bit is zero. register name: su.macwd1 register description: mac write data 1 register address: 147h
DS33Z11 ethernet mapper 113 of 169 bit # 7 6 5 4 3 2 1 0 name macwd15 macwd14 macwd13 macwd12 macwd11 macwd10 macwd09 macwd08 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 1 (macwd8-15) one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.macrwc.mcs bit is zero. register name: su.macwd2 register description: mac write data register 2 register address: 148h bit # 7 6 5 4 3 2 1 0 name macwd23 macwd22 macwd21 macwd20 macwd19 macwd18 macwd17 macwd16 0 0 0 0 0 0 0 0 bits 0 - 7: mac write data 2 (macwd16-23) one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.macrwc.mcs bit is zero. register name: su.macwd3 register description: mac write data 3 register address: 149h bit # 7 6 5 4 3 2 1 0 name macd31 macd30 macd29 macd 28 macd27 macd26 macd25 macd24 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 3 (macd24-31) one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.macrwc.mcs bit is zero. register name: su.macawl register description: mac address write low register address: 14ah bit # 7 6 5 4 3 2 1 0 name macaw 7 macaw 6 macaw 5 macaw 4 macaw3 macaw2 macaw1 macaw0 0 0 0 0 0 0 0 0 bits 0 -7: mac write address (macaw0-7) low byte of the mac address. used only for write operations. register name: su.macawh register description: mac address write high register address: 14bh bit # 7 6 5 4 3 2 1 0 name macaw 15 macaw 14 macaw 13 maca w12 macaw11 macaw10 macaw9 macaw8 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write address (macaw8-15) high byte of the mac address. used only for write operations.
DS33Z11 ethernet mapper 114 of 169 register name: su.macrwc register description: mac read write command status register address: 14ch bit # 7 6 5 4 3 2 1 0 name - - - - - - mcrw mcs default 0 0 0 0 0 0 0 0 bit 1: mac command rw (mcrw) if this bit is written to 1, a read is performed from the mac. if this bit is written to 0, a write operation is performed. address information for write operations must be located in su.macawh and su.macawl. address information for read operations must be located in su.macradh and su.macradl. the user must also write a 1 to the mcs bit, and the DS33Z11 will clear mcs when the operation is complete. bit 0: mac command status (mcs) setting mcs in conjunction with mcrw will initiate a read or write to the mac registers. upon completion of the read or write this bit is cleared. once a read or write command has been initiated the host must poll this bit to see when the operation is complete.
DS33Z11 ethernet mapper 115 of 169 register name: su.lpbk register description: ethernet interface loopb ack control register register address: 14fh bit # 7 6 5 4 3 2 1 0 name - - - - - - - qlp default 0 0 0 0 0 0 0 0 bit 0: queue loopback enable (qlp) if this bit is set to 1, data from the ethernet interface receive queue is looped back to the transmit queue. buffered data from the serial interface will remain until the loopback is removed. register name: su.gcr register description: ethernet interface general control register register address: 150h bit # 7 6 5 4 3 2 1 0 name - - - - crcs h 10s atflow jame default 0 0 0 0 0 0 1 0 bit 3: crcs if this bit is zero (default), the received mac or ethernet frame crc is stripped before the data is encapsulated and transmitted on the serial interface. data received from the serial interface is decapsulated, a crc is recalculated and appended to the packet for transmission to the ethernet interface. if this bit is set to 1, the crc is not stripped from received packets prior to encapsul ation and transmission to the serial interface, and data received from the serial interface is decapsulated directly. no crc recalculation is performed on data received from the serial interface. note that the maximum packet size supported by the ethernet interface is still 2016 (this includes the 4 bytes of crc). bit 2: h10s if this bit is set the mac will operate at 100 mbps. if this bit is zero, the mac will operate at 10 mbps. this bit controls the 10/100 selection for rmii and dce mode. in dte and mii mode, the mac determines the data rate from the incoming tx_clk and rx_clk. bit 1: automatic flow control enable (atflow) if this bit is set to 1, automatic flow control is enabled based on the connection receive queue size and high watermarks. pause frames are sent automatically in full duplex mode. the pause time must be programmed through su.macfcr. the jam sequence will not be sent automatically in half duplex mode unless the jame bit is set. this bit is applicable only in software mode. bit 0: jam enable (jame) if this bit is set to 1, a jam sequence is sent for a duration of 4 bytes. this function is only valid in half duplex mode, and will only function if automati c flow control is disabled. note that if the receive queue size is less than receive high threshold, setting a jame will jam one received frame. if jame is set and the receiver queue size is higher than the high threshold, all received frames are jammed until the queue empties below the threshold. note that su.gcr is only valid in the software mode. in hardware mode, pins are used to control automatic flow control and 100/10-speed selection.
DS33Z11 ethernet mapper 116 of 169 register name: su.tfrc register description: transmit frame resend control register address: 151h bit # 7 6 5 4 3 2 1 0 name - - - - ncfq tp dfcb tprhbc tprcb default 0 0 0 0 0 0 0 0 bit 3: no carrier queue flush bar (ncfq) if this bit is set to 1, the queue for data passing from serial interface to ethernet interface will not be flushed when loss of carrier is detected. bit 2: transmit packet deferred fail control enable (tpdfcb) if this bit if set to 1, the current frame is transmitted immediately instead of being deferred. if this bit is set to 0, the frame is deferred if crs is asserted and sent when the crs is unasserted indicating the media is idle. bit 1: transmit packet hb fail control bar (tprhbc) if this bit is set to 1, the current frame will not be retransmitted if a heartbeat failure is detected. bit 0: transmit packet resend control bar (tprcb) if this bit is set to 1, the current frame will not be retransmitted if any of the following errors have occurred: jabber time out loss of carrier excessive deferral late collision excessive collisions under run collision note that blocking retransmission due to collision (applicabl e in miii/half duplex mode) can result in unpredictable system level behavior.
DS33Z11 ethernet mapper 117 of 169 register name: su.tfsl register description: transmit frame status low register address: 152h bit # 7 6 5 4 3 2 1 0 name ur ec lc ed loc noc - fabort default 0 0 0 0 0 0 0 0 bit 7: under run (ur) when this bit is set to 1, the frame was aborted due to a data under run condition of the transmit buffer. bit 6: excessive collisions (ec) when this bit is set to 1, a frame has been aborted after 16 successive collisions while attempting to transmit the current frame. if the disable retry bit is set to 1, then excessive collisions will be set to 1 after the first collision. bit 5: late collision (lc) when this bit is set to 1, a frame was aborted by collision after the 64-bit collision window. not valid if an under run has occurred. bit 4: excessive deferral (ed) when this bit is set to 1, a frame was aborted due to excessive deferral. bit 3: loss of carrier (loc) when this bit is set to 1, a frame was aborted due to loss of carrier for one or more bit times. valid only for non-collided fram es. valid only in half-duplex operation. bit 2: no carrier (noc) when this bit is set to 1, a frame was aborted because no carrier was found for transmission. bit 1: reserved bit 0: frame abort (fabort) when this bit is set to 1, the mac has aborted a frame for one of the above reasons. when this bit is clear, the previous frame has been transmitted successfully. register name: su.tfsh register description: transmit frame status high register address: 153h bit # 7 6 5 4 3 2 1 0 name pr hbf cc3 cc2 cc1 cc0 lco def default 0 0 0 0 0 0 0 0 bit 7: packet resend (pr) when this bit is set, the current packet must be retransmitted due to a collision. bit 6: heartbeat failure (hbf) when this bit is set, the device failed to detect a heart beat after transmission. this bit is not valid if an under run has occurred. bits 2-5: collision count (cc0-3) these 4 bits indicate the number of collisions that occurred prior to successful transmission of the previous frame. not valid if excessive collisions is set to 1. bit 1: late collision (lco) when set to 1, the mac observed a collision after the 64-byte collision window. bit 0: deferred frame (def) when set to 1, the current frame was deferred due to carrier assertion by another node after being ready to transmit.
DS33Z11 ethernet mapper 118 of 169 register name: su.rfsb0 register description: receive frame status byte 0 register address: 154h bit # 7 6 5 4 3 2 1 0 name fl7 fl6 fl5 fl4 fl3 fl2 fl1 fl0 default 0 0 0 0 0 0 0 0 bits 0 - 7: frame length (fl[0:7]) these 8 bits are the low byte of the length (in bytes) of the received frame, with fcs and padding. if automatic pad stripping is enabl ed, this value is the length of the received packet without pcs or pad bytes. the upper 6 bits are contained in su.rfsb1. register name: su.rfsb1 register description: receive frame status byte 1 register address: 155h bit # 7 6 5 4 3 2 1 0 name rf wt fl13 fl12 fl11 fl10 fl9 fl8 default 0 0 0 0 0 0 0 0 bit 7: runt frame (rf) this bit is set to 1 if the received frame was altered by a collision or terminated within the collision window. bit 6: watchdog timeout (wt) this bit is set to 1 if a packet receive time exceeds 2048 byte times. after 2048 byte times the receiver is disabled and the received frame will fail crc check. bits 0-5: frame length (fl[8:13]) these 6 bits are the upper bits of the length (in bytes) of the received frame, with fcs and padding. if automatic pad stripping is enabl ed, this value is the length of the received packet without pcs or pad bytes. register name: su.rfsb2 register description: receive frame status byte 2 register address: 156h bit # 7 6 5 4 3 2 1 0 name - - crce db m iie ft cs ftl default 0 0 0 0 0 0 0 0 bit 5: crc error (crce) this bit is set to 1 if the received frame does not contain a valid crc value. bit 4: dribbling bit (db) this bit is set to 1 if the received frame contains a non-integer multiple of 8 bits. it does not indicate that the frame is invalid. this bit is not valid for runt or collided frames. bit 3: mii error (miie) this bit is set to 1 if an error was found on the mii bus. bit 2: frame type (ft) this bit is set to 1 if the received frame exceeds 1536 bytes. it is equal to zero if the received frame is an 802.3 frame. this bit is not valid for runt frames. bit 1: collision seen (cs) this bit is set to 1 if a late collision occurred on the received packet. a late collision is one that occurs after the 64-byte collision window. bit 0: frame too long (ftl) this bit is set to 1 if a frame exceeds the 1518 byte maximum standard ethernet frame. this bit is only an indication, and causes no frame truncation.
DS33Z11 ethernet mapper 119 of 169 register name: su.rfsb3 register description: receive frame status byte 3 register address: 157h bit # 7 6 5 4 3 2 1 0 name mf - - bf mcf uf cf le default 0 0 0 0 0 0 0 0 bit 7: missed frame (mf) this bit is set to 1 if the packet is not successfully received from the mac by the packet arbiter. bit 4: broadcast frame (bf) this bit is set to 1 if the current frame is a broadcast frame. bit 3: multicast frame (mcf) this bit is set to 1 if the current frame is a multicast frame. bit 2: unsupported control frame (uf) this bit is set to 1 if the frame received is a control frame with an opcode that is not supported. if the control frame bit is set, and the unsupported control frame bit is clear, then a pause frame has been received and the transmitter is paused. bit 1: control frame (cf) this bit is set to 1 when the current frame is a control frame. this bit is only valid in full-duplex mode. bit 0: length error (le) this bit is set to 1 when the frames length field and the actual byte count are unequal. this bit is only valid for 802.3 frames.
DS33Z11 ethernet mapper 120 of 169 register name: su.rmfsrl register description: receiver maximum frame low register register address: 158h bit # 7 6 5 4 3 2 1 0 name rmps7 rmps6 rmps5 rmps4 rmps3 rmps2 rmps1 rmps0 default 1 1 1 0 0 0 1 0 bits 7- 0: receiver maximum frame (rmps[0:7]) eight bits of sixteen-bit val ue. register description below. register name: su.rmfsrh register description: receiver maximum frame high register register address: 159h bit # 7 6 5 4 3 2 1 0 name rmps15 rmps14 rmps13 rmps12 rmps11 rmps10 rmps9 rmps8 default 0 0 0 0 0 1 1 1 bits 7- 0: receiver maximum frame (rmps[8:15]) this value is the receiver?s maximum frame size (in bytes), up to a maximum of 2016 bytes. any frame received greater than this value is rejected. the frame size includes destination address, source address, type/length, data and crc-32. the frame size is not the same as the frame length encoded within the ieee 802.3 frame. any values programmed that are greater than 2016 will have unpredictable behavior and should be avoided. register name: su.rqlt register description: receive queue low threshold (watermark) register address: 15ah bit # 7 6 5 4 3 2 1 0 name rqlt7 rqlt6 rqlt5 rqlt4 rqlt3 rqlt2 rqlt1 rqlt0 default 0 0 1 1 0 1 1 1 bits 0 - 7: receive queue low threshold (rqlt[0:7]) the receive queue low threshold for the connection, in increments of 32 packets of 2048 bytes each. the value of this register is multiplied by 32 * 2048 bytes to determine the byte location of the threshold. note that the receive queue is for data that was received from the ethernet interface to be sent to the serial interface. register name: su.rqht register description: receive queue high threshold (watermark) register address: 15bh bit # 7 6 5 4 3 2 1 0 name rqht7 rqht6 rqht5 rqht 4 rqht3 rqht2 rqht1 rqht0 default 0 0 1 1 1 0 1 0 bits 0 ? 7: receive queue high threshold (rqth[0:7]) the receive queue high threshold for the connection, in increments of 32 packets of 2048 bytes each. the value of this register is multiplied by 32 * 2048 bytes to
DS33Z11 ethernet mapper 121 of 169 determine the byte location of the threshold. note that the receive queue is for data that was received from the ethernet interface to be sent to the serial interface. register name: su.qrie register description: receive queue cross threshold enable register address: 15ch bit # 7 6 5 4 3 2 1 0 name - - - - rfovfie rq vfie rqltie rqhtie default 0 0 0 0 0 0 0 0 bit 3: receive fifo overflow interrupt enable (rfovfie) if this bit is set, the interrupt is enabled for rfovfls. bit 2: receive queue overflow interrupt enable (rqvfie) if this bit is set, the interrupt is enabled for rqovfls. bit 1: receive queue crosses low threshold interrupt enable (rqltie) if this bit is set, the watermark interrupt is enabled for rqlts. bit 0: receive queue crosses high threshold interrupt enable (rqhtie) if this bit is set, the watermark interrupt is enabled for rqhts. register name: su.qcrls register description: queue cross threshold latched status register address: 15dh bit # 7 6 5 4 3 2 1 0 name - - - - rfovfls r qovfls rqhtls rqltls default - - - - - - - - bit 3: receive fifo overflow latched status (rfovfls) this bit is set if the receive fifo overflows for the data to be transmitted from the mac to the sdram. bit 2: receive queue overflow latched status (rqovfls) this bit is set if the receive queue has overflowed. this register is cleared after a read. bit 1: receive queue for c onnection crossed high threshol d latched status (rqhtls) this bit is set if the receive queue crosses the high watermark. this register is cleared after a read. bit 0: receive queue for c onnection crossed low threshol d latched status (rqltls) this bit is set if the receive queue crosses the low watermark. this register is cleared after a read. note the bit order differences in the high/low thres hold indications in su.qcrls and the interrupt enables in su.qrie.
DS33Z11 ethernet mapper 122 of 169 register name: su.rfrc register description: receive frame rejection control register address: 15eh bit # 7 6 5 4 3 2 1 0 name - ucfr cfrr lerr crcerr dbr miier bfr default 0 0 0 0 0 0 0 0 bit 6: uncontrolled contro l frame reject (ucfr) when set to 1, control frames other than pause frames are allowed. when this bit is equal to zero, non-pause control frames are rejected. bit 5: control frame reject (cfrr) when set to 1, control frames are allowed. when this bit is equal to zero, all control frames are rejected. bit 4: length error reject (lerr) when set to 1, frames with an unmatched frame length field and actual number of bytes received are allowed. when equal to zero , only frames with matching length fields and actual bytes received will be allowed. bit 3: crc error reject (crcerr) when set to 1, frames received with a crc error or mii error are allowed. when equal to zero, frames with crc or mii errors are rejected. bit 2: dribbling bit reject (dbr) when set to 1, frames with lengths of non-integer multiples of 8 bits are allowed. when equal to zero, frames with dribbling bits ar e rejected. the dribbling bit setting is only valid only if there is not a collision or runt frame. bit 1: mii error reject (miier) when set to 1, frames are allowed with mii receive errors. when equal to zero, frames with mii errors are rejected. bit 0: broadcast frame reject (bfr) when set to 1, broadcast frames are allowed. when equal to zero, broadcast frames are rejected.
DS33Z11 ethernet mapper 123 of 169 9.6.2 mac registers the control registers related to the control of the individual mac?s are shown in the following table. the DS33Z11 keeps statistics for the packet traffic sent and received. the register address map is shown in the following table. note that the addresses listed are the indirect addre sses that must be provided to su.macradh/su.macradl or su.macawh/su.macawl. register name: su.maccr register description: mac control register register address: 0000h (indirect) 0000h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved hdb ps reserved reserved reserved default 0 0 0 0 0 0 0 0 0001h: bit # 23 22 21 20 19 18 17 16 name dro reserved oml0 f reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0002h: bit # 15 14 13 12 11 10 09 08 name reserved reserved reserved lcc reserved drty reserved astp default 0 0 0 0 0 0 0 0 0003h: bit # 07 06 05 04 03 02 01 00 name bolmt1 bolmt0 dc reserved te re reserved reserved default 0 0 0 0 0 0 0 0 bit 28: heartbeat disable (hdb) when set to 1, the heartbeat (sqe) function is disabled. this bit should be set to 1 when operating in mii mode. bit 27: port select (ps) this bit should be equal to 0 for proper operation. bit 23: disable receive own (dro) when set to 1, the mac disables the reception of frames while tx_en is asserted. when this bit equals zero, transmitted frames ar e also received by the mac. this bit should be cleared when operating in full-duplex mode. bit 21: loopback operating mode (omlo) when set to 1, data is looped from the transmit side, back to the receive side, without being transmitted to the phy. bit 20: full-duplex mode select (f) when set to 1, the mac transmits and receives data simultaneously. when in full-duplex mode, the heartbeat check is disabled and the heartbeat fail status should be ignored.
DS33Z11 ethernet mapper 124 of 169 bit 12: late collision control (lcc) when set to 1, enables retransmission of a collided packet even after the collision period. when this bit is clear, retransmission of late collisions is disabled. bit 10: disable retry (drty) when set to 1, the mac makes only a single attempt to transmit each frame. if a collision occurs, the mac ignores the current frame and proceeds to the next frame. when this bit equals 0, the mac will retry collided packets 16 times before signaling a retry error. bit 8: automatic pad stripping (astp) when set to 1, all incoming frames with less than 46 byte length are automatically stripped of the pad characters and fcs. bits 6 - 7: back-off limit (bolmt[0:1]) these two bits allow the user to set the back-off limit used for the maximum retransmission delay for collided packets. default operation limits the maximum delay for retransmission to a countdown of 10 bits from a random number generator. the user can reduce the maximum number of counter bits as described in the table below. see ieee 802.3 for details of the back-off algorithm. bit 7 bit 6 random number generator bits used 0 0 10 0 1 8 1 0 4 1 1 1 bit 5: deferral check (dc) when set to 1, the mac will abort packet transmission if it has deferred for more than 24,288 bit times. the deferral counter starts when the transmitter is ready to transmit a packet, but is prevented from transmission because crs is active. if the mac begins transmission but a collision occurs after the beginning of transmission, the deferral counter is reset again. if this bit is equal to zero, then the mac will defer indefinitely. bit 3: transmitter enable (te) when set to 1, packet transmission is enabled. when equal to zero, transmission is disabled. bit 2: receiver enable (re) when set to 1, packet reception is enabled. when equal to zero, packets are not received.
DS33Z11 ethernet mapper 125 of 169 register name: su.macah register description: mac address high register register address: 0004h (indirect) 0004h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 1 1 1 1 1 1 1 1 0005h: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 1 1 1 1 1 1 1 1 0006h: bit # 15 14 13 12 11 10 09 08 name padr47 padr46 padr45 padr 44 padr43 padr42 padr41 padr40 default 1 1 1 1 1 1 1 1 0007h: bit # 07 06 05 04 03 02 01 00 name padr39 padr38 padr37 padr 36 padr35 padr34 padr33 padr32 default 1 1 1 1 1 1 1 1 bits 00 ? 31: padr[32:47] these 32 bits should be initialized with the upper 4 bytes of the physical address for this mac device. register name: su.macal register description: mac address low register register address: 0008h (indirect) 0008h: bit # 31 30 29 28 27 26 25 24 name padr31 padr30 padr29 padr 28 padr27 padr26 padr25 padr24 default 1 1 1 1 1 1 1 1 0009h: bit # 23 22 21 20 19 18 17 16 name padr23 padr22 padr21 padr 20 padr19 padr18 padr17 padr16 default 1 1 1 1 1 1 1 1 000ah: bit # 15 14 13 12 11 10 09 08 name padr15 padr14 padr13 padr 12 padr11 padr10 padr09 padr08 default 1 1 1 1 1 1 1 1 000bh: bit # 07 06 05 04 03 02 01 00 name padr07 padr06 padr05 padr 04 padr03 padr02 padr01 padr00 default 1 1 1 1 1 1 1 1 bits 00 ? 31: padr[00:31] these 32 bits should be initialized with the lower 4 bytes of the physical address for this mac device.
DS33Z11 ethernet mapper 126 of 169 register name: su.macmiia register description: mac mii management (mdio) address register register address: 0014h (indirect) 0014h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0015h: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0016h: bit # 15 14 13 12 11 10 09 08 name phya4 phya3 phya2 phya1 phya0 miia4 miia3 miia2 default 0 1 0 1 1 0 1 0 0017h: bit # 07 06 05 04 03 02 01 00 name miia1 miia0 reserved reserved reserved reserved miiw miib default 1 1 0 0 0 0 0 0 bits 11 - 15: phy address (phya[0:4]) these 5 bits select one of the 32 available phy address locations to access through the phy management (mdio) bus. bits 6 - 10: mii address (miia[0:4]) - these 5 bits are the address location within the phy that is being accessed. bit 1: mii write (miiw) write this bit to 1 in order to execute a write instruction over the mdio interface. write the bit to zero to execute a read instruction. bit 0: mii busy (miib) this bit is set to 1 by the DS33Z11 during execution of a mii management instruction through the mdio interface, and is set to zero when the DS33Z11 has completed the instruction. the user should read this bit and ensure that it is equal to zero prior to beginning a mdio instruction.
DS33Z11 ethernet mapper 127 of 169 register name: su.macmiid register description: mac mii (mdio) data register register address: 0018h (indirect) 0018h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0019h: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 001ah: bit # 15 14 13 12 11 10 09 08 name miid15 miid14 miid13 miid12 miid11 miid10 miid09 miid08 default 0 0 0 0 0 0 0 0 001bh: bit # 07 06 05 04 03 02 01 00 name miid07 miid06 miid05 miid04 miid03 miid02 miid01 miid00 default 0 0 0 0 0 0 0 0 bits 0 ? 15: mii (mdio) data (miid[00:15]) these two bytes contain the data to be written to or the data read from the mii management interface (mdio).
DS33Z11 ethernet mapper 128 of 169 register name: su.macfcr register description: mac flow control register register address: 001ch (indirect) 001ch: bit # 31 30 29 28 27 26 25 24 name pt15 pt14 pt13 pt12 pt11 pt10 pt09 pt08 default 0 0 0 0 0 0 0 0 001dh: bit # 23 22 21 20 19 18 17 16 name pt07 pt06 pt05 pt04 pt03 pt02 pt01 pt00 default 0 1 0 1 0 0 0 0 001eh: bit # 15 14 13 12 11 10 09 08 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 001fh: bit # 07 06 05 04 03 02 01 00 name reserved reserved reserved reserved reserved reserved fce fcb default 0 0 0 0 0 0 1 0 bits 16 - 31: pause time (pt[00:15]) these bits are used for the pause time field in transmitted pause frames. this value is the number of time slots the remote node should wait prior to transmission. bit 1: flow control enable (fce) when set to 1, the mac automatically detects pause frames and will disable the transmitter for the requested pause time. bit 0: flow control busy (fcb) the host can set this bit to 1 in order to initiate transmission of a pause frame. during transmission of a pause frame, this bit remains set. the DS33Z11 will clear this bit when transmission of the pause frame has been completed. the user should read this bit and ensure that this bit is equal to zero prior to initiating a pause frame.
DS33Z11 ethernet mapper 129 of 169 register name: su.mmcctrl register description: mac mmc control register register address: 0100h (indirect) 0100h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0101h: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0102h: bit # 15 14 13 12 11 10 09 08 name reserved reserved mxfrm10 mxfrm9 mxfrm8 mxfrm7 mxfrm6 mxfrm5 default 0 0 1 0 1 1 1 1 0103h: bit # 07 06 05 04 03 02 01 00 name mxfrm4 mxfrm3 mxfrm2 mxfrm1 mxfrm0 reserved reserved reserved default 0 1 1 1 0 0 1 0 bits 3 - 13: maximum frame size (mxfrm[0:10]) these bits indicate the maximum packet size value. all transmitted frames larger than this value are counted as long frames. bit 1: reserved - note that this bit must be written to a ?1? for proper operation.
DS33Z11 ethernet mapper 130 of 169 register name: reserved register description: mac reserved control register register address: 010ch (indirect) 010ch: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 010dh: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 010eh: bit # 15 14 13 12 11 10 09 08 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 010fh: bit # 07 06 05 04 03 02 01 00 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 note ? addresses 10ch through 10fh must each be initialized with all 1? s (ffh) for proper software-mode operation.
DS33Z11 ethernet mapper 131 of 169 register name: reserved register description: mac reserved control register register address: 0110h (indirect) 0110h: bit # 31 30 29 28 27 26 25 24 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0111h: bit # 23 22 21 20 19 18 17 16 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0112h: bit # 15 14 13 12 11 10 09 08 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 0113h: bit # 07 06 05 04 03 02 01 00 name reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 note ? addresses 110h through 113h must each be initialized with all 1? s (ffh) for proper software-mode operation.
DS33Z11 ethernet mapper 132 of 169 register name: su.rxfrmctr register description: mac all frames received counter register address: 0200h (indirect) 0200h: bit # 31 30 29 28 27 26 25 24 name rxfrmc31 rxfrmc30 rxfrmc29 rxfrmc28 rxfrmc27 rxfrmc26 rxfrmc25 rxfrmc24 default 0 0 0 0 0 0 0 0 0201h: bit # 23 22 21 20 19 18 17 16 name rxfrmc23 rxfrmc22 rxfrmc21 rxfrmc20 rxfrmc19 rxfrmc18 rxfrmc17 rxfrmc16 default 0 0 0 0 0 0 0 0 0202h: bit # 15 14 13 12 11 10 09 08 name rxfrmc15 rxfrmc14 rxfrmc13 rxfrmc12 rxfrmc11 rxfrmc10 rxfrmc9 rxfrmc8 default 0 0 0 0 0 0 0 0 0203h: bit # 07 06 05 04 03 02 01 00 name rxfrmc7 rxfrmc6 rxfrmc5 rxfrmc4 rxfrmc3 rxfrmc2 rxfrmc1 rxfrmc0 default 0 0 0 0 0 0 0 0 bits 0 - 31: all frames received counter (rxfrmc[0:31]) 32 bit value indicating the number of frames received. each time a frame is received, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a rollover to occurring.
DS33Z11 ethernet mapper 133 of 169 register name: su.rxfrmokctr register description: mac frames received ok counter register address: 0204h (indirect) 0204h: bit # 31 30 29 28 27 26 25 24 name rxfrmok31 rxfrmok30 rxfrmok29 rxfrmok28 rxfrmok27 rxfrmok26 rxfrmok25 rxfrmok24 default 0 0 0 0 0 0 0 0 0205h: bit # 23 22 21 20 19 18 17 16 name rxfrmok23 rxfrmok22 rxfrmok21 rxfrmok20 rxfrmok19 rxfrmok18 rxfrmok17 rxfrmok16 default 0 0 0 0 0 0 0 0 0206h: bit # 15 14 13 12 11 10 09 08 name rxfrmok15 rxfrmok14 rxfrmok13 rxfrmok12 rxfrmok11 rxfrmok10 rxfrmok9 rxfrmok8 default 0 0 0 0 0 0 0 0 0207h: bit # 07 06 05 04 03 02 01 00 name rxfrmok7 rxfrmok6 rxfrmok5 rxfrmok4 rxfrmok3 rxfrmok2 rxfrmok1 rxfrmok0 default 0 0 0 0 0 0 0 0 bits 0 - 31: frames received ok counter (rxfrmok[0:31]) 32 bit value indicating the number of frames received and determined to be valid. each time a valid frame is received, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement peri od is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a rollover to occurring.
DS33Z11 ethernet mapper 134 of 169 register name: su.txfrmctr register description: mac all frames transmitted counter register address: 0300h (indirect) 0300h: bit # 31 30 29 28 27 26 25 24 name txfrmc31 txfrmc30 txfrmc29 txfrmc28 txfrmc27 txfrmc26 txfrmc25 txfrmc24 default 0 0 0 0 0 0 0 0 0301h: bit # 23 22 21 20 19 18 17 16 name txfrmc23 txfrmc22 txfrmc21 txfrmc20 txfrmc19 txfrmc18 txfrmc17 txfrmc16 default 0 0 0 0 0 0 0 0 0302h: bit # 15 14 13 12 11 10 09 08 name txfrmc15 txfrmc14 txfrmc13 txfrmc12 txfrmc11 txfrmc10 txfrmc9 txfrmc8 default 0 0 0 0 0 0 0 0 0303h: bit # 07 06 05 04 03 02 01 00 name txfrmc7 txfrmc6 txfrmc5 txfrmc4 txfrmc3 txfrmc2 txfrmc1 txfrmc0 default 0 0 0 0 0 0 0 0 bits 0 - 31: all frames transmitted counter (txfrmc[0:31]) 32 bit value indicating the number of frames transmitted. each time a frame is transmitted, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a rollover to occurring.
DS33Z11 ethernet mapper 135 of 169 register name: su.txbytesctr register description: mac all bytes transmitted counter register address: 0308h (indirect) 0308h: bit # 31 30 29 28 27 26 25 24 name txbytec31 txbytec30 txbytec29 txbytec28 txbytec27 txbytec26 txbytec25 txbytec24 default 0 0 0 0 0 0 0 0 0309h: bit # 23 22 21 20 19 18 17 16 name txbytec23 txbytec22 txbytec21 txbytec20 txbytec19 txbytec18 txbytec17 txbytec16 default 0 0 0 0 0 0 0 0 030ah: bit # 15 14 13 12 11 10 09 08 name txbytec15 txbytec14 txbytec13 txbytec12 txbytec11 txbytec10 txbytec9 txbytec8 default 0 0 0 0 0 0 0 0 030bh: bit # 07 06 05 04 03 02 01 00 name txbytec7 txbytec6 txbytec5 txbytec4 txbytec3 txbytec2 txbytec1 txbytec0 default 0 0 0 0 0 0 0 0 bits 0 - 31: all bytes transmitted counter (txbytec[0:31]) 32 bit value indicating the number of bytes transmitted. each time a byte is transmitted, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum data rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a rollover to occurring.
DS33Z11 ethernet mapper 136 of 169 register name: su.txbytesokctr register description: mac bytes transmitted ok counter register address: 030ch (indirect) 030ch: bit # 31 30 29 28 27 26 25 24 name txbyteok31 txbyteok30 txbyteok29 txbyteok28 txbyteok27 txbyteok26 txbyteok25 txbyteok24 default 0 0 0 0 0 0 0 0 030dh: bit # 23 22 21 20 19 18 17 16 name txbyteok23 txbyteok22 txbyteok21 txbyteok20 txbyteok19 txbyteok18 txbyteok17 txbyteok16 default 0 0 0 0 0 0 0 0 030eh: bit # 15 14 13 12 11 10 09 08 name txbyteok15 txbyteok14 txbyteok13 txbyteok12 txbyteok11 txbyteok10 txbyteok9 txbyteok8 default 0 0 0 0 0 0 0 0 030fh: bit # 07 06 05 04 03 02 01 00 name txbyteok7 txbyteok6 txbyteok5 txbyteok4 txbyteok3 txbyteok2 txbyteok1 txbyteok0 default 0 0 0 0 0 0 0 0 bits 0 - 31: bytes transmitted ok counter (txbyteok[0:31]) 32 bit value indicating the number of bytes transmitted and determined to be valid. each time a valid byte is transmitted, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement peri od is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a rollover to occurring.
DS33Z11 ethernet mapper 137 of 169 register name: su.txfrmundr register description: mac transmit frame under run counter register address: 0334h (indirect) 0334h: bit # 31 30 29 28 27 26 25 24 name txfrmu31 txfrmu30 txfrmu29 txfrmu28 txfrmu27 txfrmu26 txfrmu25 txfrmu24 default 0 0 0 0 0 0 0 0 0335h: bit # 23 22 21 20 19 18 17 16 name txfrmu23 txfrmu22 txfrmu21 txfrmu20 txfrmu19 txfrmu18 txfrmu17 txfrmu16 default 0 0 0 0 0 0 0 0 0336h: bit # 15 14 13 12 11 10 09 08 name txfrmu15 txfrmu14 txfrmu13 txfrmu12 txfrmu11 txfrmu10 txfrmu9 txfrmu8 default 0 0 0 0 0 0 0 0 0337h: bit # 07 06 05 04 03 02 01 00 name txfrmu7 txfrmu6 txfrmu5 txfrmu4 txfrmu3 txfrmu2 txfrmu1 txfrmu0 default 0 0 0 0 0 0 0 0 bits 0 - 31: frames aborted due to fifo under run counter (txfrmu[0:31]) 32 bit value indicating the number of frames aborted due to fifo under run. each time a frame is aborted due to fifo under run, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a rollover to occurring.
DS33Z11 ethernet mapper 138 of 169 register name: su.txbdfrmctr register description: mac all frames aborted counter register address: 0338h (indirect) 0338h: bit # 31 30 29 28 27 26 25 24 name txfrmbd31 txfrmbd30 txfrmbd29 txfrmbd28 txfrmbd27 txfrmbd26 txfrmbd25 txfrmbd24 default 0 0 0 0 0 0 0 0 0339h: bit # 23 22 21 20 19 18 17 16 name txfrmbd23 txfrmbd22 txfrmbd21 txfrmbd20 txfrmbd19 txfrmbd18 txfrmbd17 txfrmbd16 default 0 0 0 0 0 0 0 0 033ah: bit # 15 14 13 12 11 10 09 08 name txfrmbd15 txfrmbd14 txfrmbd13 txfrmbd12 txfrmbd11 txfrmbd10 txfrmbd9 txfrmbd8 default 0 0 0 0 0 0 0 0 033bh: bit # 07 06 05 04 03 02 01 00 name txfrmbd7 txfrmbd6 txfrmbd5 txfrmbd4 txfrmbd3 txfrmbd2 txfrmbd1 txfrmbd0 default 0 0 0 0 0 0 0 0 bits 0 to 31: all frames aborted counter (txfrmbd[0:31]) 32 bit value indicating the number of frames aborted due to any reason. each time a frame is aborted, this counter is incremented by 1. this counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. the user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. the user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a rollover to occurring.
DS33Z11 ethernet mapper 139 of 169 10 functional timing 10.1 functional serial i/o timing the serial interface provides flexible timing to interconnect with a wide variety of serial interfaces. tden is an input signal that can be used to enable or block the tser data. the ?shaded bits? are not clocked by the DS33Z11. the tden must occur one bit before the effected bit in the tser stream. note that polarity of the tden is selectable through li.tslcr. in the figure below, tden is active low , allowing the bits to clock and inactive high, causing the next data bit not be clocked. tclk can be gapped as shown in the following figure. similarly, the receiver function is governed by rclk i, rden and rser. rser data will not be provided to the receiver for the bits blocked when rden is inactive . the rden polarity can be programmed by li.rslcr. the rden signal must be coincident with the rser bit that needs to be blocked. figure 10-1 tx serial interface functional timing tclk gapped tser tclki tden tser tclk gapped tser figure 10-2 rx serial interface functional timing tser rclki rden rser rclk gapped rser
DS33Z11 ethernet mapper 140 of 169 the DS33Z11 provides the tbsync signal as a byte boundary indication to an external interface when x.86 (laps) functionality is selected. the functional timing of tbsync is shown in the following figure. tbsync is active high on the last bit of the byte being shifted out, and occurs every 8 bits. for the serial receiver interface, rbsync is used to provide byte boundary indication to the DS33Z11 when x.86 (laps) mode is used. the functional timing is shown in figure 10-3 . in x.86 mode, the receiver expects the rbsync byte indicator as shown in figure 10-4 . figure 10-3 transmit byte sync functional timing last bit 1st bit tclki tbysync tser figure 10-4 receive byte sync functional timing last bit 1st bit rclki rbysync rser 10.2 mii and rmii interfaces the mii interface transmit port has its own tx_clk and data interface. the data txd [3:0] operates synchronously with tx_clk. the lsb is presented first. tx_clk should be 2.5 mhz for 10 mbps operation and 25 mhz for 100 mbps operation. tx_en is valid at the same time as the first byte of the preamble. in dte mode tx_clk is input from the external phy. in dce mode, the DS33Z11 provides tx_clk, derived from an external reference (sysclki). in half-duplex (dte) mode, the DS33Z11 supports crs and col signals. crs is active when the phy detects transmit or receive activity. if there is a collision as indicated by the col input, the DS33Z11 will replace the data nibbles with jam nibbles. after a ?random? time interval, the packet is retransmitted. the mac will try to send the packet a maximum of 16 times. the jam sequence consists of 55555555h. note that the col signal and crs can be asynchronous to the tx_clk and are only valid in half duplex mode.
DS33Z11 ethernet mapper 141 of 169 figure 10-5 mii transmit functional timing txd[3:0] tx_en tx_clk p r e a e m b l e f c s figure 10-6 mii transmit half duplex with a collision functional timing txd[3:0] tx_en tx_clk p r e a m b l e j j j j j j j j crs col receive data (rxd[3:0]) is clocked from the external phy synchronously with rx_clk. the rx_clk signal is 2.5 mhz for 10 mbps operation and 25 mhz for 100 mbps operation. rx_dv is asserted by the phy from the first nibble of the preamble in 100 mbps operation or first ni bble of sfd for 10 mbps operation. the data on rxd[3:0] is not accepted by the mac if rx_dv is low or rx_err is high (in dte mode). rx_err should be tied low when in dce mode. figure 10-7 mii receive functional timing rxd[3:0] rx_clk p r e a e m b l e f c s in rmii mode, tx_en is high with the first bit of the preamble. the txd[1:0] is synchronous with the 50 mhz ref_clk. for 10 mbps operation, the data bit outputs are updated every 10 clocks . figure 10-8 rmii transmit interface functional timing txd[1:0] tx_en refclk p r e a m b l e f c s
DS33Z11 ethernet mapper 142 of 169 rmii receive data on rxd[1:0] is expected to be synchronous with the rising edge of the 50 mhz ref_clk. the data is only valid if crs_dv is high. the external phy asynchronously drives crs_dv low during carrier loss. figure 10-9 rmii receive interface functional timing rxd[1:0] crs_dv refclk p r e a m b l e f c s 10.3 spi interface mode and eeprom program sequence the DS33Z11 will act as an spi master when configured with modec[1:0] to read the configuration from an external serial eeprom, such as the atmel at25160a. the eeprom must be programmed with the data structure shown in table 10-1 . the mosi (master out slave in) signal can be selectively output on the rising or falling edge of spick. the miso data can be sampled on rising or falling edge of spick based on the ckpha pin input. the spick is generated by the DS33Z11 at a frequency of 8.33 mhz, derived from an external sysclki of 100 mhz. the initialization sequence is commenced immediately after power up reset or a rising edge of the rst input pin. the spi master initiates a read with the instruction code 0000x011b; followed by the address location. the spi_cs is held low until the data addressed is read and latched. the DS33Z11 begins reading the eeprom at address 0000h. data is sequentially latched until the last data byte is read and latched. the indirect mac registers require a special program sequence at the end of the eeprom file. four mac registers can be programmed in the eeprom mode: su.maccr, su.macmiia, su.macmiid, and su.macfcr. all other indirect mac registers do not need to be initialized for eeprom mode operation. the indirect mac registers are programmed using four separat e seven-byte records from the eeprom. an example is shown in table 10-2 . figure 10-10 spi master functional timing mosi spick ckpha=0 0 0 0 0 x 0 1 1 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 spi_cs* 0 0 0 0 miso 01234567891011202122232425262728293031 spick ckpha=1
DS33Z11 ethernet mapper 143 of 169 table 10-1 eeprom program memory map functional block address range for data in eeprom (in hex) global registers 000 to 03f arbiter registers 040 to 07f bert registers 080 to 0bf serial interface tx registers 0c0 to 0ff serial interface rx registers 100 to 13f ethernet interface registers 140 to 17f mac register write 1 180 to 186 (special for indirect addresses) mac register write 2 187 to 18d (special for indirect addresses) mac register write 3 18e to 194 (special for indirect addresses) mac register write 4 195 to 19b (special for indirect addresses) table 10-2 eeprom program sequence and example for indirect mac registers eeprom file byte function eeprom memory location example eeprom address location example data, using mac register write 1 to initialize maccr mac data byte 1 base + 00h 180h 2ch - written to su.macwd0 mac data byte 2 base + 01h 181h 00h - written to su.macwd1 mac data byte 3 base + 02h 182h 04h - written to su.macwd2 mac data byte 4 base + 03h 183h 90h - written to su.macwd3 mac address low base + 04h 184h 00h - written to su.macawl mac address high base + 05h 185h 00h - written to su.macawh mac write command base + 06h 186h 01h - written to su.macrwc to initiate the indirect write note: base eeprom addre ss of mac instructions = 180h
DS33Z11 ethernet mapper 144 of 169 11 operating parameters absolute maximum ratings voltage range on any lead with respect to v ss (except v dd )????????????????..?0.5v to +5.5v supply voltage range (vdd3.3) with respect to v ss ????????????????????..?0.3v to +3.6v supply voltage range (vdd1.8) with respect to v ss ????????????????????..?0.3v to +2.0v ambient operating temperat ure range?????????????????????????...?40c to +85c junction operating temperat ure range?????????????????????????.?40c to +125c storage temperature r ange??????????????????????????????.?55c to +125c soldering temperatur e??????????????????????see ipc/jedec j-st d-020 specification these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. ambient operating temperature range is assuming the device is mounted on a jedec standard test board in a convection-cooled jed ec test enclosure. note: the ?typ? values listed below are not production tested. table 11-1 recommended dc operating conditions (vdd3.3 = 3.3v 5%,vdd1.8 = 1.8 5% t j = -40c to +85c.) parameter symbol conditions min typ max units logic 1 v ih 2.0 3.465 v logic 0 v il -0.3 +0.8 v supply (vdd3.3) 5% vdd3.3 3.135 3.300 3.465 v supply (vdd1.8) 5% vdd1.8 1.71 1.8 1.89 v table 11-2 dc electrical characteristics (vdd3.3 = 3.3v 5%,vdd1.8 = 1.8 5% t j = -40c to +85c.) parameter symbol conditions min typ max units i/o supply current (vdd3.3 = 3.465v) i ddio (notes 1, 2) 25 ma core supply current (vdd1.8 = 1.89) i ddcore (notes 1, 2) 30 ma power-down current (all disable and power-down bits set) i ddd (note 2) 90 ma lead capacitance c io 7 pf input leakage i il -10 +10 a input leakage i ilp -50 -10 a output leakage (when hi-z) i lo -10 +10 a output voltage (i oh = -4.0ma) v oh all outputs 2.4 v output voltage (i ol = +4.0ma) v ol all outputs 0.4 v output voltage (i oh = -8.0ma) v oh ref_clko 2.4 v output voltage (i ol = +12.0ma) v ol tser 0.4 v v il 0.8 v input voltage v ih 2.0 v note 1: typical power is 145mw. note 2: all outputs loaded with rated capacitance; all inputs between v dd and v ss ; inputs with pullups connected to v dd .
DS33Z11 ethernet mapper 145 of 169 11.1 thermal characteristics parameter min typ max ambient temperature (note 1) -40 c +85 c junction temperature +125 c theta-ja ( ja ) in still air for 169-pin 14mm csbga (note 2) +52.7 c/w theta-ja ( ja ) in still air for 100-pin 10mm csbga (note 2) +47.1 c/w note 1: the package is mounted on a four-layer jedec standard test board. note 2: theta-ja ( ja ) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer jedec standard test board. 11.2 theta-ja vs. airflow theta-ja air flow (m/s) 169-pin 14mm csbga (c/w) 100-pin 10mm csbga (c/w) 0 52.7 47.1 1 45.8 40.8 2.5 43.8 38.4
DS33Z11 ethernet mapper 146 of 169 11.3 transmit mii interface 10 mbps 100 mbps parameter symbol min typ max min typ max units tx_clk period t1 400 40 ns tx_clk low time t2 140 260 14 26 ns tx_clk high time t3 140 260 14 26 ns tx_clk to txd, tx_en delay t4 0 20 0 20 ns figure 11-1 transmit mii interface tx_clk txd[3:0] tx_en t4 t4 t2 t3 t1
DS33Z11 ethernet mapper 147 of 169 11.4 receive mii interface 10 mbps 100 mbps parameter symbol min typ max min typ max units rx_clk period t5 400 40 ns rx_clk low time t6 140 260 14 26 ns rx_clk high time t7 140 260 14 26 ns rxd, rx_dv to rx_clk setup time t8 5 5 ns rx_clk to rxd, rx_dv hold time t9 5 5 ns figure 11-2 receive mii interface timing t8 t9 rx_clk rxd[3:0] rx_dv t8 t9 t5 t6 t7
DS33Z11 ethernet mapper 148 of 169 11.5 transmit rmii interface 10 mbps 100 mbps parameter symbol min typ max min typ max units ref_clk frequency 50mhz, 50ppm 50mhz, 50ppm ref_clk period t1 20 20 ns ref_clk low time t2 7 13 7 13 ns ref_clk high time t3 7 13 7 13 ns ref_clk to txd, tx_en delay t4 5 10 5 10 ns figure 11-3 transmit rmii interface ref_clk txd[1:0] tx_en t4 t4 t2 t3 t1
DS33Z11 ethernet mapper 149 of 169 11.6 receive rmii interface 10 mbps 100 mbps parameter symbol min typ max min typ max units ref_clk frequency 50mhz, 50ppm 50mhz, 50ppm ref_clk period t1 20 20 ns ref_clk low time t2 7 13 7 13 ns ref_clk high time t3 7 13 7 13 ns rxd, crs_dv to ref_clk setup time t8 5 5 ns ref_clk to rxd, crs_dv hold time t9 5 5 ns figure 11-4 receive rmii interface timing t8 t9 ref_clk rxd[3:0] crs_dv t8 t9 t5 t6 t7
DS33Z11 ethernet mapper 150 of 169 11.7 mdio interface parameter symbol min typ max units mdc frequency 1.67 mhz mdc period t1 540 600 660 ns mdc low time t2 270 300 330 ns mdc high time t3 270 300 330 ns mdc to mdio output delay t4 20 10 ns mdio setup time t5 10 ns mdio hold time t6 20 ns figure 11-5 mdio timing mdc mdio t4 mdc t2 t3 t1 mdio t5 t6
DS33Z11 ethernet mapper 151 of 169 11.8 transmit wan interface parameter symbol min typ max units tclki frequency 52 mhz tclki period t1 19.2 ns tclki low time t2 8 ns tclki high time t3 8 ns tclki to tser output delay t4 10 ns tsync setup time t5 7 ns tsync hold time t6 7 ns figure 11-6 transmit wan timing tclki t2 t3 t1 tser t4 tsync t5 t6
DS33Z11 ethernet mapper 152 of 169 11.9 receive wan interface parameter symbol min typ max units rclki frequency 52 mhz rclki period t1 19.2 ns rclki low time t2 8 ns rclki high time t3 8 ns rser setup time t4 7 ns rden setup time t4 7 ns rbsync setup time t4 7 ns rden setup time t4 7 ns rbsync setup time t4 7 ns rser hold time t5 2 ns rbsync hold time t5 2 ns rden hold time t5 2 ns rbsync hold time t5 2 ns figure 11-7 receive wan timing rclki t2 t3 t1 rser rden t4 t5 t4 t5 rbsync t4 t5
DS33Z11 ethernet mapper 153 of 169 11.10 sdram timing table 11-3 sdram interface timing 100 mhz parameter symbol min typ max units sdclko period t1 9.7 10 10.3 ns sdclko duty cycle t2 4 6 ns sdclko to sdata valid; write to sdram t3 7 ns sdclko to sdata drive on; write to sdram t4 4 ns sdclko to sdata invalid; write to sdram t5 3 ns sdclko to sdata drive off; write to sdram t6 4 ns sdata to sdclko setup time; read from sdram t7 2 ns sdclko to sdata hold time; read from sdram t8 2 ns sdclko to sras , scas , swe , sdcs active; read or write to sdram t9 5 ns sdclko to sras , scas , swe , sdcs inactive; read or write to sdram t10 2 ns sdclko to sda, sba valid; read or write to sdram t11 7 ns sdclko to sda, sba invalid; read or write to sdram t12 2 ns sdclko to sdmask valid; read or write to sdram t13 5 ns sdclko to sdmask invalid; read or write to sdram t14 2 ns
DS33Z11 ethernet mapper 154 of 169 figure 11-8 sdram interface timing sdclko (output) sdata (output) t1 sdata (input) sras, scas, swe, sdcs (output) t2 t3 t5 t6 t7 t8 t10 t9 sda, sba (output) sdmask (output) t4 t12 t11 t14 t13
DS33Z11 ethernet mapper 155 of 169 11.11 ac characteristics?microprocessor bus timing (vdd3.3 = 3.3v 5%, vdd1.8 = 1.8 5%; t j = -40c to +85c.) parameter symbol min typ max units setup time for a[12:0] valid to cs active t1 0 ns setup time for cs active to either rd or wr active t2 0 ns delay time from either rd or ds active to data[7:0] valid t3 75 ns hold time from either rd or wr inactive to cs inactive t4 0 ns hold time from cs or rd or ds inactive to data[7:0] tri-state t5 5 20 ns wait time from r w active to latch data t6 80 ns data setup time to ds active t7 10 ns data hold time from r w inactive t8 2 ns address hold from r w inactive t9 0 ns write access to subsequent write/read access delay time t10 80 ns
DS33Z11 ethernet mapper 156 of 169 figure 11-9 intel bus read timing (hwmode = 0, modec = 00) t2 t3 address valid data valid t4 t9 t5 t10 addr[12:0] data[7:0] cs rd wr t1 figure 11-10 intel bus write timing (hwmode = 0, modec = 00) t2 t6 address valid t4 t9 t10 addr[12:0] data[7:0] cs rd wr t7 t8 t1
DS33Z11 ethernet mapper 157 of 169 figure 11-11 motorola bus read timing (hwmode = 0, modec = 01) t2 t3 address valid data valid t4 t9 t5 t10 addr[12:0] data[7:0] cs ds rw t1 figure 11-12 motorola bus write timing (hwmode = 0, modec = 01) t2 t6 address valid t4 t9 t10 addr[12:0] data[7:0] cs rw ds t7 t8 t1
DS33Z11 ethernet mapper 158 of 169 11.12 eeprom interface timing parameter symbol min typ max units spick period t1 120 ns spick low time t2 55 65 ns spick high time t3 55 65 ns mosi setup delay t4 50 ns miso hold t5 50 ns miso setup t6 10 ns miso hold t7 10 ns spi_cs hold t8 60 ns figure 11-13 eeprom interface timing mosi miso spi_cs t1 t2 t3 t5 t6 t8 t4 t7 ?
DS33Z11 ethernet mapper 159 of 169 11.13 jtag interface timing (vdd3.3 = 3.3v 5%, vdd1.8 = 1.8 5%; t j = -40c to +85c.) parameter symbol min typ max units jtclk clock period t1 1000 ns jtclk clock high: low time (note 1) t2:t3 50 500 ns jtclk to jtdi, jtms setup time t4 2 ns jtclk to jtdi, jtms hold time t5 2 ns jtclk to jtdo delay t6 2 50 ns jtclk to jtdo hiz delay t7 2 50 ns jtrst width low time t8 100 ns note 1: clock can be stopped high or low. figure 11-14 jtag interface timing diagram jtclk t1 jtd0 t4 t5 t2 t3 t7 jtdi, jtms t6 jtrst t8
DS33Z11 ethernet mapper 160 of 169 12 jtag information the device supports the standard instruction codes sample:preload, bypass, and extest. optional public instructions included are highz, clamp, and idcode. see table 12-1 . the DS33Z11 contains the following as required by ieee 1149.1 standard test access port and boundary scan architecture. test access port (tap) tap controller instruction register bypass register boundary scan register device identification register the test access port has the necessary interface pins: jtrst , jtclk, jtms, jtdi, and jtdo. see the pin descriptions for details. refer to ieee 1149.1-1990, ieee 1149.1a-1993, and ieee 1149.1b-1994 for details about the boundary scan architecture and the test access port. figure 12-1 jtag functional block diagram 12.1 jtag tap controller state machine description this section covers the details on the operation of the te st access port (tap) controller state machine. the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk. boundary scan register identification register bypass register instruction register test access port controller mux select tri-state jtdi 10k jtms 10k jtclk jtrst 10k jtdo
DS33Z11 ethernet mapper 161 of 169 tap controller state machine the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk. see figure 12-2 for a diagram of the state machine operation. test-logic-reset upon power-up, the tap controller is in the test-logic-reset state. the instruction register will contain the idcode instruction. all system logic of the device will operate normally. run-test-idle the run-test-idle is used between scan operations or during specific tests. the instruction register and test registers will remain idle. select-dr-scan all test registers retain their previous state. with jtms low, a rising edge of jtclk moves the controller into the capture-dr state and will initiate a scan sequence. jtms high during a rising edge on jtclk moves the controller to the select-ir-scan state. capture-dr data may be parallel-loaded into the test data registers selected by the current instruction. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. on the rising edge of jtclk, the controller will go to the shift-dr state if jtms is low or it will go to the exit1-dr state if jtms is high. shift-dr the test data register selected by the current instruction is connected between jtdi and jtdo and will shift data one stage towards its serial output on each rising edge of jtclk. if a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. exit1-dr while in this state, a rising edge on jtclk will put the c ontroller in the update-dr state, which terminates the scanning process, if jtms is high. a rising edge on jtclk with jtms low will put the controller in the pause- dr state. pause-dr shifting of the test registers is halted while in this state. all test registers selected by the current instruction will retain their previous state. the controller will remain in this state while jtms is low. a rising edge on jtclk with jtms high will put the controller in the exit2-dr state. exit2-dr a rising edge on jtclk with jtms high while in this state will put the controller in the update-dr state and terminate the scanning process. a rising edge on jtclk with jtms low will enter the shift-dr state.
DS33Z11 ethernet mapper 162 of 169 update-dr a falling edge on jtclk while in the update-dr state will latch the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output due to changes in the shift register. select-ir-scan all test registers retain their previous state. the inst ruction register will remain unchanged during this state. with jtms low, a rising edge on jtclk moves the controller into the capture-ir state and will initiate a scan sequence for the instruction register. jtms high during a rising edge on jtclk puts the controller back into the test-logic-reset state. capture -ir the capture-ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the rising edge of jtclk, the controller will enter the exit1-ir state. if jtms is low on the rising edge of jtclk, the controller will enter the shift-ir state. shift-ir in this state, the shift register in the instruction register is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk towards the serial output. the parallel register, as well as all test registers, remains at their previous states. a rising edge on jtclk with jtms high will move the controller to the exit1-ir state. a rising edge on jtclk with jtms low will keep the controller in the shift-ir state while moving data one stage thorough the instruction shift register. exit1-ir a rising edge on jtclk with jtms low will put the controller in the pause-ir state. if jtms is high on the rising edge of jtclk, the controller will enter the update-ir state and terminate the scanning process. pause-ir shifting of the instruction shift register is halted temporarily. with jtms high, a rising edge on jtclk will put the controller in the exit2-ir state. the controller will remain in the pause-ir state if jtms is low during a rising edge on jtclk. exit2-ir a rising edge on jtclk with jtms low will put the controlle r in the update-ir state. the controller will loop back to shift-ir if jtms is high during a rising edge of jtclk in this state. update-ir the instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on jtclk with jtms held low will put the controller in the run-test-idle state. with jtms high, the controller will enter the select-dr-scan state.
DS33Z11 ethernet mapper 163 of 169 figure 12-2 tap controller state diagram 12.2 instruction register the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift-ir state, the instruction shift register is connected between jtdi and jtdo. while in the shift-ir state, a rising edge on jtclk with jtms low will shift the data one stage towards the serial output at jtdo. a rising edge on jtclk in the exit1-ir state or the exit2-ir state with jtms high will move the controller to the update-ir state. the falling edge of that same jtclk will latch the data in the instruction shift register to the instruction parallel output. instructi ons supported by the DS33Z11 and its respective operational binary codes are shown in table 12-1 . 1 0 0 1 11 1 1 1 1 1 11 1 1 00 0 0 0 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0
DS33Z11 ethernet mapper 164 of 169 table 12-1 instruction codes for ieee 1149.1 architecture instruction selected regi ster instruction codes sample:preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 highz bypass 100 idcode device identification 001 12.2.1 sample:preload this is a mandatory instruction for the ieee 1149.1 specification. this instruction supports two functions. the digital i/os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the capture-dr state. sample:preload also allows the device to shift data into the boundary scan register via jtdi using the shift-dr state. 12.2.2 bypass when the bypass instruction is latched into the parallel instruction register, jtdi connects to jtdo through the one-bit bypass test register. this allows data to pass from jtdi to jtdo not affecting the device?s normal operation. 12.2.3 extest this allows testing of all interconnections to the device. when the extest instruction is latched in the instruction register, the following actions occur. once enabled via the u pdate-ir state, the parallel outputs of all digital output pins are driven. the boundary scan register is connected between jtdi and jtdo. the capture-dr will sample all digital inputs into the boundary scan register. 12.2.4 clamp all digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between jtdi and jtdo. the outputs will not change during the clamp instruction. 12.2.5 highz all digital outputs of the device are placed in a high-impedance state. the bypass register is connected between jtdi and jtdo. 12.2.6 idcode when the idcode instruction is latched into the parallel instruction register, the identification test register is selected. the device identification code is loaded into the identification register on the rising edge of jtclk following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially via jtdo. during test-logic-reset, the identification code is forced into the instruction register?s parallel output. the id code will always have a ?1? in the lsb position. the next 11 bits identify the manufacturer?s jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
DS33Z11 ethernet mapper 165 of 169 12.3 jtag id codes table 12-2 id code structure device revision id[31:28] device code id[27:12] manufacturer?s code id[11:1] required id[0] DS33Z11 0000 0000 0000 0110 0001 000 1010 0001 1 12.4 test registers ieee 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. an optional test register has been included with the DS33Z11 design. this test register is the identification register and is used in conjunction with the idcode instruction and the test-logic-reset state of the tap controller. 12.5 boundary scan register this register contains both a shift register path and a latched parallel output for all control cells and digital i/o cells and is n bits in length. 12.6 bypass register this is a single one-bit shift register used in conjunction with the bypass, clamp, and highz instructions, which provides a short path between jtdi and jtdo. 12.7 identification register the identification register contains a 32-bit shift regi ster and a 32-bit latched parallel output. this register is selected during the idcode instruction and when the tap controller is in the test-logic-reset state. 12.8 jtag functional timing this functional timing for the jtag circuits shows: the jtag controller starting from reset state shifting out the first 4 lsb bits of the idcode shifting in the bypass instruction (111) while shifting out the mandatory x01 pattern shifting the tdi pin to the tdo pin through the bypass shift register an asynchronous reset occurs while shifting
DS33Z11 ethernet mapper 166 of 169 figure 12-3 jtag functional timing jtclk jtrst jtms jtdi jtdo (state) reset x run test idle select dr scan capture dr shift dr exit1 dr update dr select dr scan select ir scan capture ir shift ir exit1 ir update ir select dr scan capture dr shift dr test logic idle (inst) idcode bypass idcode x x x x x output pin output pin level change if in "extest" instruction mode
DS33Z11 ethernet mapper 167 of 169 13 package information (the package drawing(s) in this data sheet may not reflect t he most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallasp ackinfo .) 13.1 package outline drawing of 169-ball csbga (view from bottom of device) bottom view
DS33Z11 ethernet mapper 168 of 169 13.2 package outline drawing of 100-ball csbga (ds33zh11 only) 0.36 0.05 0.36 0.05 0.70 0.05 1.42
DS33Z11 ethernet mapper 169 of 169 maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entir ely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconducto r reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa are registered trademarks of maxim integrated products, inc., and dallas semiconductor corporation. 14 revision history revision description 021805 new product release

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